diff --git a/src/soc/intel/elkhartlake/chip.h b/src/soc/intel/elkhartlake/chip.h
index d4bb04ff75..e7593f8d14 100644
--- a/src/soc/intel/elkhartlake/chip.h
+++ b/src/soc/intel/elkhartlake/chip.h
@@ -238,6 +238,9 @@ struct soc_intel_elkhartlake_config {
 	/* PCIe RP L1 substate */
 	enum L1_substates_control PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS];
 
+	/* PCIe ModPhy related */
+	struct pcie_modphy_config pcie_mp_cfg[CONFIG_MAX_ROOT_PORTS];
+
 	/* PCIe root port maximum payload size, default is set to 128 bytes. */
 	enum {
 		RpMaxPayload_128,
diff --git a/src/soc/intel/elkhartlake/romstage/fsp_params.c b/src/soc/intel/elkhartlake/romstage/fsp_params.c
index d05a94d2aa..71bd473ca8 100644
--- a/src/soc/intel/elkhartlake/romstage/fsp_params.c
+++ b/src/soc/intel/elkhartlake/romstage/fsp_params.c
@@ -22,6 +22,8 @@ enum {
 static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
 		const struct soc_intel_elkhartlake_config *config)
 {
+	size_t i;
+
 	/*
 	 * If IGD is enabled, set IGD stolen size to 60MB.
 	 * Otherwise, skip IGD init in FSP.
@@ -33,6 +35,40 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
 	m_cfg->SaGv = config->SaGv;
 	m_cfg->RMT = config->RMT;
 
+	/* PCIe ModPhy configuration */
+	for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) {
+		if (config->pcie_mp_cfg[i].tx_gen1_downscale_amp_override) {
+			m_cfg->PchPcieHsioTxGen1DownscaleAmpEnable[i] = 1;
+			m_cfg->PchPcieHsioTxGen1DownscaleAmp[i] =
+					config->pcie_mp_cfg[i].tx_gen1_downscale_amp;
+		}
+		if (config->pcie_mp_cfg[i].tx_gen2_downscale_amp_override) {
+			m_cfg->PchPcieHsioTxGen2DownscaleAmpEnable[i] = 1;
+			m_cfg->PchPcieHsioTxGen2DownscaleAmp[i] =
+					config->pcie_mp_cfg[i].tx_gen2_downscale_amp;
+		}
+		if (config->pcie_mp_cfg[i].tx_gen3_downscale_amp_override) {
+			m_cfg->PchPcieHsioTxGen3DownscaleAmpEnable[i] = 1;
+			m_cfg->PchPcieHsioTxGen3DownscaleAmp[i] =
+					config->pcie_mp_cfg[i].tx_gen3_downscale_amp;
+		}
+		if (config->pcie_mp_cfg[i].tx_gen1_de_emph) {
+			m_cfg->PchPcieHsioTxGen1DeEmphEnable[i] = 1;
+			m_cfg->PchPcieHsioTxGen1DeEmph[i] =
+					config->pcie_mp_cfg[i].tx_gen1_de_emph;
+		}
+		if (config->pcie_mp_cfg[i].tx_gen2_de_emph_3p5) {
+			m_cfg->PchPcieHsioTxGen2DeEmph3p5Enable[i] = 1;
+			m_cfg->PchPcieHsioTxGen2DeEmph3p5[i] =
+					config->pcie_mp_cfg[i].tx_gen2_de_emph_3p5;
+		}
+		if (config->pcie_mp_cfg[i].tx_gen2_de_emph_6p0) {
+			m_cfg->PchPcieHsioTxGen2DeEmph6p0Enable[i] = 1;
+			m_cfg->PchPcieHsioTxGen2DeEmph6p0[i] =
+					config->pcie_mp_cfg[i].tx_gen2_de_emph_6p0;
+		}
+	}
+
 	m_cfg->PcieRpEnableMask = pcie_rp_enable_mask(pch_rp_groups);
 
 	FSP_ARRAY_LOAD(m_cfg->PcieClkSrcUsage, config->PcieClkSrcUsage);