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Falco/Slippy: Patch to remove redundant graphics initializations

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gma_fui_init repeats the initializations already performed in gma_setup_panel.
These redundant initializations reset any gtt settings done before this call.
Hence, they had to be done again after call to gma_fui_init. However, the call
gma_fui_init is not required at all. Does not affect the behavior of suspend/resume.

BUG=None
BRANCH=None
TEST=Built and booted on falco in normal and developer mode. Graphics init works fine.
Suspend/resume tested successfully

Change-Id: Idfb9f9930624694b878ddc0fe8648b3c8dd80e55
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/65997
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
This commit is contained in:
Furquan Shaikh 2013-08-15 15:23:58 -07:00 • committed by ChromeBot
commit c376aea1b8
1 changed files with 0 additions and 82 deletions
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82
src/mainboard/google/slippy/gma.c
View file

@ -161,87 +161,6 @@ static void palette(void)
}
}
/* this is code known to be needed for FUI, and useful
* but not essential otherwise. At some point, we hope,
* it's always going to be on. It gets the chip
* into a known good state
* -- including turning on the power well --
* which we're not sure is being done correctly.
* Does it belong here? It belongs somewhere in the
* northbridge, that we know.
*/
static void gma_fui_init(int noisy)
{
printk(BIOS_SPEW, "pci dev(0x0,0x2,0x0,0x8)");
printk(BIOS_SPEW, "pci dev(0x0,0x1f,0x0,0x10)");
printk(BIOS_SPEW, "pci dev(0x0,0x2,0x0,0x0)");
printk(BIOS_SPEW, "pci dev(0x0,0x2,0x0,0x2)");
printk(BIOS_SPEW, "pci dev(0x0,0x1f,0x0,0x0)");
printk(BIOS_SPEW, "pci dev(0x0,0x1f,0x0,0x2)");
io_i915_write32(0x80000000,0x45400);
intel_dp_wait_reg(0x00045400, 0xc0000000);
printk(BIOS_SPEW, "pci dev(0x0,0x0,0x0,0x14)");
printk(BIOS_SPEW, "pci dev(0x0,0x2,0x0,0x17)");
printk(BIOS_SPEW, "pci dev(0x0,0x2,0x0,0x18)");
io_i915_write32(0x00000000,_CURACNTR);
io_i915_write32((/* DISPPLANE_SEL_PIPE(0=A,1=B) */0x0<<24)|0x00000000,_DSPACNTR);
io_i915_write32(0x00000000,_DSPBCNTR);
io_i915_write32(0x8000298e,CPU_VGACNTRL);
io_i915_write32(0x00000000,_DSPASIZE+0xc);
io_i915_write32(0x00000000,_DSPBSURF);
io_i915_write32( DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SCRAMBLING_DISABLE_IRONLAKE | DP_SYNC_VS_HIGH |0x00000091,DP_A);
io_i915_write32(0x00200090,_FDI_RXA_MISC);
io_i915_write32(0x0a000000,_FDI_RXA_MISC);
io_i915_write32(0x00000070,0x46408);
io_i915_write32(0x04000000,0x42090);
io_i915_write32(0x00000000,0x9840);
io_i915_write32(0xa4000000,0x42090);
io_i915_write32(0x00001000,SOUTH_DSPCLK_GATE_D);
io_i915_write32(0x00004000,0x42080);
io_i915_write32(0x00ffffff,0x64f80);
io_i915_write32(0x0007000e,0x64f84);
io_i915_write32(0x00d75fff,0x64f88);
io_i915_write32(0x000f000a,0x64f8c);
io_i915_write32(0x00c30fff,0x64f90);
io_i915_write32(0x00060006,0x64f94);
io_i915_write32(0x00aaafff,0x64f98);
io_i915_write32(0x001e0000,0x64f9c);
io_i915_write32(0x00ffffff,0x64fa0);
io_i915_write32(0x000f000a,0x64fa4);
io_i915_write32(0x00d75fff,0x64fa8);
io_i915_write32(0x00160004,0x64fac);
io_i915_write32(0x00c30fff,0x64fb0);
io_i915_write32(0x001e0000,0x64fb4);
io_i915_write32(0x00ffffff,0x64fb8);
io_i915_write32(0x00060006,0x64fbc);
io_i915_write32(0x00d75fff,0x64fc0);
io_i915_write32(0x001e0000,0x64fc4);
io_i915_write32(0x00ffffff,DDI_BUF_TRANS_A);
io_i915_write32(0x0006000e,DDI_BUF_TRANS_A+0x4);
io_i915_write32(0x00d75fff,DDI_BUF_TRANS_A+0x8);
io_i915_write32(0x0005000a,DDI_BUF_TRANS_A+0xc);
io_i915_write32(0x00c30fff,DDI_BUF_TRANS_A+0x10);
io_i915_write32(0x00040006,DDI_BUF_TRANS_A+0x14);
io_i915_write32(0x80aaafff,DDI_BUF_TRANS_A+0x18);
io_i915_write32(0x000b0000,DDI_BUF_TRANS_A+0x1c);
io_i915_write32(0x00ffffff,DDI_BUF_TRANS_A+0x20);
io_i915_write32(0x0005000a,DDI_BUF_TRANS_A+0x24);
io_i915_write32(0x00d75fff,DDI_BUF_TRANS_A+0x28);
io_i915_write32(0x000c0004,DDI_BUF_TRANS_A+0x2c);
io_i915_write32(0x80c30fff,DDI_BUF_TRANS_A+0x30);
io_i915_write32(0x000b0000,DDI_BUF_TRANS_A+0x34);
io_i915_write32(0x00ffffff,DDI_BUF_TRANS_A+0x38);
io_i915_write32(0x00040006,DDI_BUF_TRANS_A+0x3c);
io_i915_write32(0x80d75fff,DDI_BUF_TRANS_A+0x40);
io_i915_write32(0x000b0000,DDI_BUF_TRANS_A+0x44);
io_i915_write32( DIGITAL_PORTA_HOTPLUG_ENABLE |0x00000010,DIGITAL_PORT_HOTPLUG_CNTRL);
io_i915_write32( PORTD_HOTPLUG_ENABLE | PORTB_HOTPLUG_ENABLE |0x10100010,SDEISR+0x30);
io_i915_write32((PCH_PP_UNLOCK&0xabcd0000)| EDP_FORCE_VDD |0xabcd0008,PCH_PP_CONTROL);
mdelay(200);
io_i915_write32(0x0004af06,PCH_PP_DIVISOR);
/* we may need more but let's see. */
}
void dp_init_dim_regs(struct intel_dp *dp);
void dp_init_dim_regs(struct intel_dp *dp)
{
@ -397,7 +316,6 @@ int i915lightup(unsigned int pphysbase, unsigned int piobase,
dp->aux_clock_divider = 0xe1;
dp->precharge = 3;
gma_fui_init(0);
//intel_prepare_ddi_buffers(0, 0);
//ironlake_edp_panel_vdd_on(dp);
dp->address = 0x50;