From c3265da0058efb19ea6e3d914b5edb54baee0ee5 Mon Sep 17 00:00:00 2001 From: Jarried Lin Date: Tue, 17 Dec 2024 19:02:07 +0800 Subject: [PATCH] soc/mediatek/mt8196: Add pwrsel driver The MediaTek pwrsel (Power Select) is mainly used to reduce power consumption, controlled by mcupm. BUG=b:317009620 TEST=Build pass Change-Id: Ib1b8588810fdad5c675dee865627337269b57d18 Signed-off-by: Jarried Lin Reviewed-on: https://review.coreboot.org/c/coreboot/+/85613 Tested-by: build bot (Jenkins) Reviewed-by: Yidi Lin Reviewed-by: Yu-Ping Wu --- src/soc/mediatek/mt8196/Makefile.mk | 1 + .../mediatek/mt8196/include/soc/addressmap.h | 1 + .../mediatek/mt8196/include/soc/mtk_pwrsel.h | 18 +++++++++++++ src/soc/mediatek/mt8196/mtk_pwrsel.c | 27 +++++++++++++++++++ 4 files changed, 47 insertions(+) create mode 100644 src/soc/mediatek/mt8196/include/soc/mtk_pwrsel.h create mode 100644 src/soc/mediatek/mt8196/mtk_pwrsel.c diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk index 2e78e1ad07..b61f7d929b 100644 --- a/src/soc/mediatek/mt8196/Makefile.mk +++ b/src/soc/mediatek/mt8196/Makefile.mk @@ -34,6 +34,7 @@ romstage-y += ../common/memory_test.c romstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c romstage-y += ../common/mt6363.c mt6363.c romstage-y += ../common/mt6373.c mt6373.c +romstage-y += mtk_pwrsel.c romstage-y += ../common/pmif_clk.c pmif_clk.c romstage-y += ../common/pmif.c pmif_init.c romstage-y += pmif_spmi.c diff --git a/src/soc/mediatek/mt8196/include/soc/addressmap.h b/src/soc/mediatek/mt8196/include/soc/addressmap.h index dc21f60c3b..fcb5fc85c9 100644 --- a/src/soc/mediatek/mt8196/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8196/include/soc/addressmap.h @@ -8,6 +8,7 @@ enum { MCUPM_CFG_BASE = 0x0C240000, BUS_TRACE_MONITOR_BASE = 0x0D040000, IO_PHYS = 0x10000000, + MFGSYS_BASE = 0x40000000, }; enum { diff --git a/src/soc/mediatek/mt8196/include/soc/mtk_pwrsel.h b/src/soc/mediatek/mt8196/include/soc/mtk_pwrsel.h new file mode 100644 index 0000000000..327735e169 --- /dev/null +++ b/src/soc/mediatek/mt8196/include/soc/mtk_pwrsel.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#ifndef __SOC_MEDIATEK_MT8196_MTK_PWRSEL__ +#define __SOC_MEDIATEK_MT8196_MTK_PWRSEL__ + +#include + +#define VAL_PWRSEL 0x0 +#define VAL_PWRSEL_AUTO_MODE 0x1FF0000 +#define OFFSET_PWRSEL 0x04A0 +#define OFFSET_PWRSEL_AUTO_MODE_CFG 0x04A4 + +#define MFG_VCORE_AO_CFG_BASE (MFGSYS_BASE + 0x0B860000) /* 0x4B860000 */ +#define MFG_VCORE_AO_RPC_PWRSEL_CONFIG (MFG_VCORE_AO_CFG_BASE + 0x00B4) /* 0x4B8600B4 */ + +void pwrsel_init(void); + +#endif /* end of __SOC_MEDIATEK_MT8196_MTK_PWRSEL__ */ diff --git a/src/soc/mediatek/mt8196/mtk_pwrsel.c b/src/soc/mediatek/mt8196/mtk_pwrsel.c new file mode 100644 index 0000000000..b1cb52865c --- /dev/null +++ b/src/soc/mediatek/mt8196/mtk_pwrsel.c @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#include +#include +#include + +static void cpu_pwrsel_init(void) +{ + write32p(MCUSYS_BASE + OFFSET_PWRSEL, VAL_PWRSEL); + write32p(MCUSYS_BASE + OFFSET_PWRSEL_AUTO_MODE_CFG, VAL_PWRSEL_AUTO_MODE); +} + +static void gpu_pwrsel_init(void) +{ + write32p(MFG_VCORE_AO_RPC_PWRSEL_CONFIG, GENMASK(14, 0)); +} + +void pwrsel_init(void) +{ + cpu_pwrsel_init(); + gpu_pwrsel_init(); + + /* PWR_SEL must be 0x0 */ + printk(BIOS_DEBUG, "PWR_SEL = %#x\n", read32p(MCUSYS_BASE + OFFSET_PWRSEL)); + /* PWRSEL_CONFIG must be 0x7fff */ + printk(BIOS_DEBUG, "PWRSEL_CONFIG = %#x\n", read32p(MFG_VCORE_AO_RPC_PWRSEL_CONFIG)); +}