From c25337dac8c3ecdd8ffe5b4d11acebb216132405 Mon Sep 17 00:00:00 2001 From: David Hendricks Date: Thu, 21 Nov 2013 17:03:51 -0800 Subject: [PATCH] tegra124: Bump up HCLK and PCLK This sets the sclk:hclk:pclk ratio to 1:2:2 which allows faster transfers from peripherals to memory. Performance-wise this currently decreases ramstage loading time by about 20ms and payload loading time by 35ms. BUG=chrome-os-partner:24182 BRANCH=none TEST=Built and booted on Nyan rev 1 and 0. No longer see long delays in between bytes when transferring >64 bytes via SPI. CQ-DEPEND=CL:177578 Change-Id: I5812122bf6312a1ab490945c6e52fa3372e86fc9 Signed-off-by: David Hendricks Reviewed-on: https://chromium-review.googlesource.com/177563 Reviewed-by: Tom Warren Reviewed-by: Julius Werner --- src/soc/nvidia/tegra124/clock.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/src/soc/nvidia/tegra124/clock.c b/src/soc/nvidia/tegra124/clock.c index 2cf5b77c0a..ab5547f4f7 100644 --- a/src/soc/nvidia/tegra124/clock.c +++ b/src/soc/nvidia/tegra124/clock.c @@ -395,9 +395,10 @@ void clock_init(void) setbits_le32(&clk_rst->pllc_misc, PLLC_MISC_LOCK_ENABLE); while (!(read32(&clk_rst->pllc_base) & PLL_BASE_LOCK)) /* wait */; - /* APB pclk and AHB hclk derive from sclk, let's not overkill them */ - write32(3 << HCLK_DIVISOR_SHIFT | 3 << PCLK_DIVISOR_SHIFT, - &clk_rst->clk_sys_rate); /* pclk = hclk/4 = sclk/16 */ + /* Typical ratios are 1:2:2 or 1:2:3 sclk:hclk:pclk (See: APB DMA + * features section in the TRM). */ + write32(1 << HCLK_DIVISOR_SHIFT | 0 << PCLK_DIVISOR_SHIFT, + &clk_rst->clk_sys_rate); /* pclk = hclk = sclk/2 */ write32(0 << SCLK_DIVIDEND_SHIFT | (div_round_up(TEGRA_PLLC_KHZ, 300000) - 1) << SCLK_DIVISOR_SHIFT | SCLK_DIV_ENB, &clk_rst->super_sclk_div);