From c238b87bcd9d35afd828476d6ee88322ac5d0f88 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Sat, 19 Oct 2013 03:53:42 -0700 Subject: [PATCH] Tegra124: SDMMC: Take the SDMMC 3 and 4 out of reset and ungate their clocks. These are attached to the SD card and the EMMC on nyan. BUG=None TEST=Built and booted into depthcharge on nyan. With changes that configure these controllers there, saw the driver attempt (and fail) to read data from the device instead of just hanging. BRANCH=None Change-Id: Idf82adc9e8708388d2ad77fca00e224af0fe7661 Signed-off-by: Gabe Black Reviewed-on: https://chromium-review.googlesource.com/173793 Reviewed-by: Gabe Black Tested-by: Gabe Black Commit-Queue: Gabe Black --- src/soc/nvidia/tegra124/clock.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/src/soc/nvidia/tegra124/clock.c b/src/soc/nvidia/tegra124/clock.c index 5f9ee49c1a..f3b43a718c 100644 --- a/src/soc/nvidia/tegra124/clock.c +++ b/src/soc/nvidia/tegra124/clock.c @@ -266,11 +266,13 @@ void clock_config(void) { /* Enable clocks for the required peripherals. */ setbits_le32(&clk_rst->clk_out_enb_l, - CLK_L_CACHE2 | CLK_L_GPIO | CLK_L_TMR | CLK_L_I2C1); + CLK_L_CACHE2 | CLK_L_GPIO | CLK_L_TMR | CLK_L_I2C1 | + CLK_L_SDMMC4); setbits_le32(&clk_rst->clk_out_enb_h, CLK_H_EMC | CLK_H_I2C2 | CLK_H_I2C5 | CLK_H_SBC1 | CLK_H_PMC | CLK_H_APBDMA | CLK_H_MEM); - setbits_le32(&clk_rst->clk_out_enb_u, CLK_U_I2C3 | CLK_U_CSITE); + setbits_le32(&clk_rst->clk_out_enb_u, + CLK_U_I2C3 | CLK_U_CSITE | CLK_U_SDMMC3); setbits_le32(&clk_rst->clk_out_enb_v, CLK_V_MSELECT); setbits_le32(&clk_rst->clk_out_enb_w, CLK_W_DVFS); @@ -300,11 +302,13 @@ void clock_config(void) /* Take required peripherals out of reset. */ clrbits_le32(&clk_rst->rst_dev_l, - CLK_L_CACHE2 | CLK_L_GPIO | CLK_L_TMR | CLK_L_I2C1); + CLK_L_CACHE2 | CLK_L_GPIO | CLK_L_TMR | CLK_L_I2C1 | + CLK_L_SDMMC4); clrbits_le32(&clk_rst->rst_dev_h, CLK_H_EMC | CLK_H_I2C2 | CLK_H_I2C5 | CLK_H_SBC1 | CLK_H_PMC | CLK_H_APBDMA | CLK_H_MEM); - clrbits_le32(&clk_rst->rst_dev_u, CLK_U_I2C3 | CLK_U_CSITE); + clrbits_le32(&clk_rst->rst_dev_u, + CLK_U_I2C3 | CLK_U_CSITE | CLK_U_SDMMC3); clrbits_le32(&clk_rst->rst_dev_v, CLK_V_MSELECT); clrbits_le32(&clk_rst->rst_dev_w, CLK_W_DVFS); }