From c13eadeadb0a1054bc0bef3dc6002fed2a093f57 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Tue, 8 Jul 2025 08:25:27 +0200 Subject: [PATCH] soc/amd/common/block/psp/psp_smi_flash: Fix busy check The busy check is only supported on Fam 17h Picasso and Raven Ridge. On other platforms the register might not exist and the bits always read as ones. This prevents the PSP SMI handler from accessing the SPI flash. TEST: Ensured that the code does not block on 1Ah platforms. Signed-off-by: Patrick Rudolph Change-Id: I063b7cd66a5058ae558ad36e4a7dd89a48f718a7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/88356 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Alicja Michalska --- src/soc/amd/common/block/psp/psp_smi_flash.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/src/soc/amd/common/block/psp/psp_smi_flash.c b/src/soc/amd/common/block/psp/psp_smi_flash.c index a32ba217d2..9f9f31d94c 100644 --- a/src/soc/amd/common/block/psp/psp_smi_flash.c +++ b/src/soc/amd/common/block/psp/psp_smi_flash.c @@ -94,10 +94,15 @@ static enum mbox_p2c_status find_psp_spi_flash_device_region(uint64_t target_nv_ static bool spi_controller_busy(void) { - const bool busy = (spi_read8(SPI_MISC_CNTRL) & SPI_SEMAPHORE_DRIVER_LOCKED); + bool busy = false; - if (busy) - printk(BIOS_NOTICE, "PSP: SPI controller busy\n"); + if (CONFIG(SOC_AMD_PICASSO)) { + // Only implemented on Picasso and Raven Ridge + busy = (spi_read8(SPI_MISC_CNTRL) & SPI_SEMAPHORE_DRIVER_LOCKED); + + if (busy) + printk(BIOS_NOTICE, "PSP: SPI controller busy\n"); + } return busy; }