From c0e22d76d3887ca1f727443a47db38dec12c0b74 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Tue, 22 Oct 2013 06:01:30 -0700 Subject: [PATCH] Set the EC SPI clock source to PLLP and divide down to around 5MHz BUG=None TEST=Built and booted into depthcharge. Saw that the AP could communicate with the EC over SPI. BRANCH=None Change-Id: Ib19a8e543a96a0614a97afc6e795496b1bdfc8b4 Signed-off-by: Gabe Black Reviewed-on: https://chromium-review.googlesource.com/173954 Reviewed-by: Gabe Black Commit-Queue: Gabe Black Tested-by: Gabe Black --- src/mainboard/google/nyan/bootblock.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mainboard/google/nyan/bootblock.c b/src/mainboard/google/nyan/bootblock.c index 33cd49410e..78e6d070a7 100644 --- a/src/mainboard/google/nyan/bootblock.c +++ b/src/mainboard/google/nyan/bootblock.c @@ -43,6 +43,8 @@ static void set_clock_sources(void) clock_configure_source(i2c4, CLK_M, 1333); clock_configure_source(i2c5, CLK_M, 1333); + clock_configure_source(sbc1, PLLP, 5000); + /* UARTA gets PLLP, deactivate CLK_UART_DIV_OVERRIDE */ writel(PLLP << CLK_SOURCE_SHIFT, &clk_rst->clk_src_uarta);