diff --git a/src/soc/mediatek/common/dp/include/soc/dptx_reg_v2.h b/src/soc/mediatek/common/dp/include/soc/dptx_reg_v2.h index da0654ab9d..d1f4f411ef 100644 --- a/src/soc/mediatek/common/dp/include/soc/dptx_reg_v2.h +++ b/src/soc/mediatek/common/dp/include/soc/dptx_reg_v2.h @@ -157,7 +157,6 @@ #define REG_3F44_DP_ENC_4P_3 0x3F44 #define PHY_PWR_STATE_OW_EN_DP_ENC_4P_3 BIT(2) #define PHY_PWR_STATE_OW_EN_DP_ENC_4P_3_MASK BIT(2) -#define BIAS_POWER_ON (0x01 << 3) #define PHY_PWR_STATE_OW_VALUE_DP_ENC_4P_3_MASK GENMASK(4, 3) #define REG_3F80_DP_ENC_4P_3 0x3F80 #define PSR_PATGEN_AVT_EN_FLDMASK 0x20 diff --git a/src/soc/mediatek/mt8189/include/soc/dptx_reg.h b/src/soc/mediatek/mt8189/include/soc/dptx_reg.h index af2e6a131e..b65d6c2bed 100644 --- a/src/soc/mediatek/mt8189/include/soc/dptx_reg.h +++ b/src/soc/mediatek/mt8189/include/soc/dptx_reg.h @@ -5,6 +5,7 @@ #include +#define BIAS_POWER_ON (0x03 << 3) #define DP_PHY_DIG_TX_CTL_0 0x1444 #define RGS_AUX_LDO_EN_READY_MASK BIT(0) #define DRIVING_FORCE 0x18 diff --git a/src/soc/mediatek/mt8196/include/soc/dptx_reg.h b/src/soc/mediatek/mt8196/include/soc/dptx_reg.h index df7a29630a..a26328dd24 100644 --- a/src/soc/mediatek/mt8196/include/soc/dptx_reg.h +++ b/src/soc/mediatek/mt8196/include/soc/dptx_reg.h @@ -5,6 +5,7 @@ #include +#define BIAS_POWER_ON (0x01 << 3) #define DP_PHY_DIG_TX_CTL_0 0x1474 #define RGS_AUX_LDO_EN_READY_MASK BIT(1) #define DRIVING_FORCE 0x30