From c026a3fb861e157f1e17a121fc2ef70b903f36f2 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Sat, 19 Oct 2013 03:17:25 -0700 Subject: [PATCH] Tegra124: Take the SPI1 controller out of reset and enable its clock. This controller is used to communicate with the EC on nyan. BUG=None TEST=Built and booted into depthcharge on nyan. With this and other changes, saw that basic communication with the EC over the SPI bus was possible, although it didn't work perfectly. BRANCH=None Change-Id: I6f487a97b299d4aff4b00e43d8005ded29d8204b Signed-off-by: Gabe Black Reviewed-on: https://chromium-review.googlesource.com/173787 Reviewed-by: David Hendricks Commit-Queue: Gabe Black Tested-by: Gabe Black --- src/soc/nvidia/tegra124/clock.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/nvidia/tegra124/clock.c b/src/soc/nvidia/tegra124/clock.c index 2ea930eb30..5f9ee49c1a 100644 --- a/src/soc/nvidia/tegra124/clock.c +++ b/src/soc/nvidia/tegra124/clock.c @@ -268,7 +268,7 @@ void clock_config(void) setbits_le32(&clk_rst->clk_out_enb_l, CLK_L_CACHE2 | CLK_L_GPIO | CLK_L_TMR | CLK_L_I2C1); setbits_le32(&clk_rst->clk_out_enb_h, - CLK_H_EMC | CLK_H_I2C2 | CLK_H_I2C5 | + CLK_H_EMC | CLK_H_I2C2 | CLK_H_I2C5 | CLK_H_SBC1 | CLK_H_PMC | CLK_H_APBDMA | CLK_H_MEM); setbits_le32(&clk_rst->clk_out_enb_u, CLK_U_I2C3 | CLK_U_CSITE); setbits_le32(&clk_rst->clk_out_enb_v, CLK_V_MSELECT); @@ -302,7 +302,7 @@ void clock_config(void) clrbits_le32(&clk_rst->rst_dev_l, CLK_L_CACHE2 | CLK_L_GPIO | CLK_L_TMR | CLK_L_I2C1); clrbits_le32(&clk_rst->rst_dev_h, - CLK_H_EMC | CLK_H_I2C2 | CLK_H_I2C5 | + CLK_H_EMC | CLK_H_I2C2 | CLK_H_I2C5 | CLK_H_SBC1 | CLK_H_PMC | CLK_H_APBDMA | CLK_H_MEM); clrbits_le32(&clk_rst->rst_dev_u, CLK_U_I2C3 | CLK_U_CSITE); clrbits_le32(&clk_rst->rst_dev_v, CLK_V_MSELECT);