From bfeef0cc455e783a3ed56f40c5f816dfb973d2c4 Mon Sep 17 00:00:00 2001 From: Jeremy Compostella Date: Tue, 12 Nov 2024 10:32:43 -0800 Subject: [PATCH] soc/intel/pantherlake: Bind SoC config VR settings to respective UPD This commit binds the cep_enable, enable_fast_vmode and fast_vmode_i_trip voltage regulator SoC settings to the CepEnable, EnableFastVmode and IccLimit UPDs respectively. BUG=b:357011633 TEST=CepEnable, EnableFastVmode and IccLimit are set accordingly Change-Id: Ie72e4725cb97b4af7843a43eeaedd687d28b6752 Signed-off-by: Jeremy Compostella Reviewed-on: https://review.coreboot.org/c/coreboot/+/85131 Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) Reviewed-by: Pranava Y N --- src/soc/intel/pantherlake/romstage/fsp_params.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/pantherlake/romstage/fsp_params.c b/src/soc/intel/pantherlake/romstage/fsp_params.c index 93c8777d82..b5fc93bc66 100644 --- a/src/soc/intel/pantherlake/romstage/fsp_params.c +++ b/src/soc/intel/pantherlake/romstage/fsp_params.c @@ -285,8 +285,15 @@ static void fill_fspm_thermal_params(FSP_M_CONFIG *m_cfg, static void fill_fspm_vr_config_params(FSP_M_CONFIG *m_cfg, const struct soc_intel_pantherlake_config *config) { - for (size_t i = 0; i < ARRAY_SIZE(m_cfg->EnableFastVmode); i++) - m_cfg->EnableFastVmode[i] = 0; + for (size_t i = 0; i < ARRAY_SIZE(config->enable_fast_vmode); i++) { + if (config->cep_enable[i]) { + m_cfg->CepEnable[i] = config->cep_enable[i]; + if (config->enable_fast_vmode[i]) { + m_cfg->EnableFastVmode[i] = config->enable_fast_vmode[i]; + m_cfg->IccLimit[i] = config->fast_vmode_i_trip[i]; + } + } + } } #if CONFIG(PLATFORM_HAS_EARLY_LOW_BATTERY_INDICATOR)