New files for dlel 350
This commit is contained in:
Ronald G. Minnich
parent
49b1718724
commit
bd557f33aa
3 changed files with 291 additions and 0 deletions
55
src/mainboard/dell/350/Config
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55
src/mainboard/dell/350/Config
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northbridge intel/440bx
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southbridge intel/piix4e
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nsuperio SMC/fdc37b807
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option ENABLE_FIXED_AND_VARIABLE_MTRRS
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option PIIX4_DEVFN=0x38
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option NO_KEYBOARD
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option ZKERNEL_START=0xfffc0000
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option ZKERNEL_MASK=0x7f
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option L440BX
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object mainboard.o
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cpu p6
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cpu p5
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makerule phlash_floppy: phlash ; mcopy -o /tmp/$(PHLASH_BASE_NAME).bi? a:
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makerule phlash: $(BOOT_IMAGE) linuxbios.rom headers ; rm -f xa?
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addaction phlash split -b 64k $(BOOT_IMAGE)
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addaction phlash # Now just touch them if we have a really
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addaction phlash # small kernel!
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addaction phlash touch xaa xab xac xad xae xaf xag xah
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addaction phlash # this is starting at bank 4, and proceeding on. Unused banks are dups
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addaction phlash # the nvram is odd, all of the banks are interleaved
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addaction phlash cat $(PHLASH_BASE_NAME).bi1.header xaa > $(PHLASH_BASE_NAME).bi1 #4
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addaction phlash cat $(PHLASH_BASE_NAME).bi3.header xab > $(PHLASH_BASE_NAME).bi3 #6
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addaction phlash cat $(PHLASH_BASE_NAME).bi2.header xac > $(PHLASH_BASE_NAME).bi2 #7
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addaction phlash cat $(PHLASH_BASE_NAME).bi4.header xad > $(PHLASH_BASE_NAME).bi4 #9
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addaction phlash cat $(PHLASH_BASE_NAME).bi7.header xae > $(PHLASH_BASE_NAME).bi7 #a
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addaction phlash cat $(PHLASH_BASE_NAME).bi6.header xaf > $(PHLASH_BASE_NAME).bi6 #b
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addaction phlash cat $(PHLASH_BASE_NAME).bi9.header xag > $(PHLASH_BASE_NAME).bi9 #c
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addaction phlash cat $(PHLASH_BASE_NAME).bi8.header xah > $(PHLASH_BASE_NAME).bi8 #d
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addaction phlash cat $(PHLASH_BASE_NAME).bia.header linuxbios.rom > $(PHLASH_BASE_NAME).bia
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addaction phlash # Part o & 5 seem not to be written reliably for some reason...
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addaction phlash cat $(PHLASH_BASE_NAME).bio.header /dev/null > $(PHLASH_BASE_NAME).bio
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addaction phlash cat $(PHLASH_BASE_NAME).bi5.header /dev/null > $(PHLASH_BASE_NAME).bi5
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addaction phlash sh -x $(TOP)/src/mainboard/intel/l440bx/BUILD_PHLASH_FILES $(PHLASH_BASE_NAME)
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makerule headers : $(PHLASH_BASE_NAME).bi1.header $(PHLASH_BASE_NAME).bi2.header $(PHLASH_BASE_NAME).bi3.header $(PHLASH_BASE_NAME).bi4.header $(PHLASH_BASE_NAME).bi5.header $(PHLASH_BASE_NAME).bi6.header $(PHLASH_BASE_NAME).bi7.header $(PHLASH_BASE_NAME).bi8.header $(PHLASH_BASE_NAME).bi9.header $(PHLASH_BASE_NAME).bia.header $(PHLASH_BASE_NAME).bio.header ;
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makerule $(PHLASH_BASE_NAME).bi1.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi1 ; dd if=$< of=$@ bs=1 count=160
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makerule $(PHLASH_BASE_NAME).bi2.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi2 ; dd if=$< of=$@ bs=1 count=160
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makerule $(PHLASH_BASE_NAME).bi3.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi3 ; dd if=$< of=$@ bs=1 count=160
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makerule $(PHLASH_BASE_NAME).bi4.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi4 ; dd if=$< of=$@ bs=1 count=160
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makerule $(PHLASH_BASE_NAME).bi5.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi5 ; dd if=$< of=$@ bs=1 count=160
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makerule $(PHLASH_BASE_NAME).bi6.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi6 ; dd if=$< of=$@ bs=1 count=160
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makerule $(PHLASH_BASE_NAME).bi7.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi7 ; dd if=$< of=$@ bs=1 count=160
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makerule $(PHLASH_BASE_NAME).bi8.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi8 ; dd if=$< of=$@ bs=1 count=160
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makerule $(PHLASH_BASE_NAME).bi9.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi9 ; dd if=$< of=$@ bs=1 count=160
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makerule $(PHLASH_BASE_NAME).bia.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bia ; dd if=$< of=$@ bs=1 count=160
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makerule $(PHLASH_BASE_NAME).bio.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bio ; dd if=$< of=$@ bs=1 count=160
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addaction clean rm -f $(PHLASH_BASE_NAME)* xa?
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216
src/mainboard/dell/350/ipl_3com905.S
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src/mainboard/dell/350/ipl_3com905.S
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/*
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* ipl.S: Initial Program Loader (IPL) for SiS 630 and M-System DoC Millennium
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*
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*
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* Copyright 2000 Silicon Integrated Systems Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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*
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* Reference:
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* 1. SiS 630 Specification
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* 2. System Management Bus Specification Rev 1.1
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* 3. PC SDRAM Serial Presence Detect (SPD) Specification Rev 1.2B
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* 4. Booting From the DiskOnChip Millennium, M-Systems Application Note Ap-DOC-044
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* APR-2000, 93-SR-001-44-7L REV. 1.0
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*
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* $Id$
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*/
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#include "ipl.h"
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.code16
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.org 0xfe00
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dell350_3com905_start:
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cli # Disables the maskable
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# hardware interrupts.
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movw %cs, %ax # makes data segment ==
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movw %ax, %ds # code segment
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# move the eip to eax, then mask off the bits,
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# so we have an address for the docipl. This address is used
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# to diddle the docipl so we can read blocks.
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# enable writes on the docipl.
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init_complete:
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sis630ipl_start:
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/* O.K. we have DRAM now, so set up STACK for CALL/RET */
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movw $DOC_STACK_SEG, %ax
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movw %ax, %ss
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movw $SPL_RAM_SEG, %ax
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movw %ax, %es
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#ifdef STD_FLASH
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movw $0xf000, %ax
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movw %ax, %ds
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xorw %sp, %sp # clear %sp
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xorw %si, %si
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xorw %di, %di
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movw $0xffff, %cx
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rep
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movsb
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movw $DOC_WIN_SEG, %ax
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movw %ax, %ds
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#else
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movw $sis950_init_table, %si # unlock SiS 950 LPC
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movw $0x05, %cx # select Clock Selection
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movw $0x2e, %dx # and Flash ROM I/F
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rep
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outsb
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movb $0xfd, %al # enable write, CLKIN = 24 MHZ
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outb %al, $0x2f
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xorw %sp, %sp # clear %sp
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xorw %dx, %dx # clear %dx, start of RAM
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movw $0x800, %si # point %si to CDSN Data area
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movw $0x1000, %di # point %di to CDSN Control area
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movw $DOC_SPL_START_BLK, %bp # start page of LinuxBIOS
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movb $0x84, %al # Reset DOC Millennium
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call doc_reset
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movb $0x85, %al # Turn into Normal Mode
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call doc_reset
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read_next_page:
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movw $0x1000, %di # point %di to CDSN Control area
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flash_command:
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movb $0x03, 0x04(%di) # start command cycle
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movb $0x00, (%si) # issue flash command Read00
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call doc_cycle_end
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movw %bp, %bx # %bp is current page number
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flash_address:
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shll $0x08, %ebx
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movb $0x03, %cl # this one is DANGEROUS but I am
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# sure the upper 3 bytes == 0x00
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movb $0x05, 0x04(%di) # start address cycle
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0:
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movb %bl, (%si) # write address to CDSNIO
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shrw $0x08, %bx # shift next address byte
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loop 0b
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call doc_cycle_end
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wait_for_flash_ready:
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/* delay by reding NOP register before polling the FLASH READY bit,
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this is inlined to save a call/ret pair */
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doc_delay:
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movb $0x04, %cl # this one is DANGEROUS but I am
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# sure the upper 3 bytes == 0x00
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0:
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movb 0x20(%di), %al # read DOC NOP retisger
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loop 0b # four times
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testb $0x80, 0x04(%di) # is flash ready ?
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jz wait_for_flash_ready
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movb 0x1d(%di), %al # init read pipeline
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movw $0x100, %cx # 1 page = 512 bytes
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movw $0x800, %si # point %si to CDSN Data area
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movw %dx, %di # restore saved current destination
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rep
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movsw
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movw %di, %dx # save current destination
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incw %bp # increse current page number
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cmpw $128, %bp # moved 63 KB ??
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jl read_next_page # no, read next page
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#endif /*else STD_FLASH */
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sis630ipl_end:
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jmp spl_vector # jump to SPL vector
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/* ------------------------------------------------------------------------------------------*/
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write_lpc_register:
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/* Input: AH - register number. AL - register value. */
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movl $LPC_BRIDGE_BASE_ADDR, %edx
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jmp write_common
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write_pci_register:
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/* Input: AH - register number. AL - register value. */
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movl $NORTH_BRIDGE_BASE_ADDR, %edx
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write_common:
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movw %ax, %cx # Save %ax to %cx.
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movzbl %ch, %eax # add register address to
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addl %edx, %eax # PCI base address
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movw $PCI_COMMAND_PORT, %dx
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outl %eax, %dx
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movw $PCI_DATA_PORT, %dx
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andb $0x03, %al
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addb %al, %dl
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movb %cl, %al
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outb %al, %dx
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RET_SP # End of write_[lpc|pci]_reg
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read_spd:
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/* Input: AH = 05h, AL = byte number of SPD to be read.
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Output: BL = The value of specified SPD byte. */
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movb $0x05, %ah
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CALL_BP(sis_set_smbus)
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movw $0x0312, %ax # Start, R/W byte Data
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CALL_BP(sis_set_smbus)
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wait_for_smbus_read:
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movb $0x80, %dl # Read SMBus status
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inb %dx, %al
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testb $0x02, %al # if device errors
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jnz read_spd_fail # then skip read SPD
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testb $0x08, %al # if not complete
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jz wait_for_smbus_read # then wait SPD data complete
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read_spd_fail:
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movb $0x08, %ah
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doc_reset:
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/* Input: AL = value write to DOC_CONTROL register
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Clobberd: CX */
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movb %al, 0x02(%di) # write DoC Control retister
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movb %al, 0x02(%di) # twice
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ret # End of doc_reset
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doc_cycle_end:
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movb $0x00, 0x1e(%di) # flush write pepeline
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movb $0x01, 0x04(%di) # end command cycle
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ret
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reset_vector:
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# .byte 0xea # jmp to fe00:0000, where IPL
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# .word 0x0000, DOC_WIN_SEG # starts in DoC
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.byte 0xea # jmp to fe00:0000, where IPL
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.word 0xfe00, 0xf000 # starts in DoC
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spl_vector:
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.byte 0xea # jmp to 8000:0000, where SPL
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.word 0x0000, SPL_RAM_SEG # (LinuxBIOS) starts in RAM
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end:
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hlt
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20
src/mainboard/dell/350/mainboard.c
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20
src/mainboard/dell/350/mainboard.c
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#include <printk.h>
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void
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mainboard_fixup(void)
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{
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}
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void
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final_mainboard_fixup(void)
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{
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void final_southbridge_fixup(void);
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void final_superio_fixup(void);
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printk(KERN_INFO "DELL 350\n");
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final_southbridge_fixup();
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#ifndef USE_NEW_SUPERIO_INTERFACE
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final_superio_fixup();
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#endif
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}
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