From bd557f33aa3dd100e8ce33c61f862483621fde1c Mon Sep 17 00:00:00 2001 From: "Ronald G. Minnich" Date: Fri, 6 Jul 2001 23:13:48 +0000 Subject: [PATCH] New files for dlel 350 --- src/mainboard/dell/350/Config | 55 +++++++ src/mainboard/dell/350/ipl_3com905.S | 216 +++++++++++++++++++++++++++ src/mainboard/dell/350/mainboard.c | 20 +++ 3 files changed, 291 insertions(+) create mode 100644 src/mainboard/dell/350/Config create mode 100644 src/mainboard/dell/350/ipl_3com905.S create mode 100644 src/mainboard/dell/350/mainboard.c diff --git a/src/mainboard/dell/350/Config b/src/mainboard/dell/350/Config new file mode 100644 index 0000000000..8d5f2382ff --- /dev/null +++ b/src/mainboard/dell/350/Config @@ -0,0 +1,55 @@ +northbridge intel/440bx +southbridge intel/piix4e + +nsuperio SMC/fdc37b807 + +option ENABLE_FIXED_AND_VARIABLE_MTRRS +option PIIX4_DEVFN=0x38 +option NO_KEYBOARD +option ZKERNEL_START=0xfffc0000 +option ZKERNEL_MASK=0x7f +option L440BX + +object mainboard.o + +cpu p6 +cpu p5 + +makerule phlash_floppy: phlash ; mcopy -o /tmp/$(PHLASH_BASE_NAME).bi? a: + +makerule phlash: $(BOOT_IMAGE) linuxbios.rom headers ; rm -f xa? +addaction phlash split -b 64k $(BOOT_IMAGE) +addaction phlash # Now just touch them if we have a really +addaction phlash # small kernel! +addaction phlash touch xaa xab xac xad xae xaf xag xah +addaction phlash # this is starting at bank 4, and proceeding on. Unused banks are dups +addaction phlash # the nvram is odd, all of the banks are interleaved +addaction phlash cat $(PHLASH_BASE_NAME).bi1.header xaa > $(PHLASH_BASE_NAME).bi1 #4 +addaction phlash cat $(PHLASH_BASE_NAME).bi3.header xab > $(PHLASH_BASE_NAME).bi3 #6 +addaction phlash cat $(PHLASH_BASE_NAME).bi2.header xac > $(PHLASH_BASE_NAME).bi2 #7 +addaction phlash cat $(PHLASH_BASE_NAME).bi4.header xad > $(PHLASH_BASE_NAME).bi4 #9 +addaction phlash cat $(PHLASH_BASE_NAME).bi7.header xae > $(PHLASH_BASE_NAME).bi7 #a +addaction phlash cat $(PHLASH_BASE_NAME).bi6.header xaf > $(PHLASH_BASE_NAME).bi6 #b +addaction phlash cat $(PHLASH_BASE_NAME).bi9.header xag > $(PHLASH_BASE_NAME).bi9 #c +addaction phlash cat $(PHLASH_BASE_NAME).bi8.header xah > $(PHLASH_BASE_NAME).bi8 #d +addaction phlash cat $(PHLASH_BASE_NAME).bia.header linuxbios.rom > $(PHLASH_BASE_NAME).bia +addaction phlash # Part o & 5 seem not to be written reliably for some reason... +addaction phlash cat $(PHLASH_BASE_NAME).bio.header /dev/null > $(PHLASH_BASE_NAME).bio +addaction phlash cat $(PHLASH_BASE_NAME).bi5.header /dev/null > $(PHLASH_BASE_NAME).bi5 +addaction phlash sh -x $(TOP)/src/mainboard/intel/l440bx/BUILD_PHLASH_FILES $(PHLASH_BASE_NAME) + +makerule headers : $(PHLASH_BASE_NAME).bi1.header $(PHLASH_BASE_NAME).bi2.header $(PHLASH_BASE_NAME).bi3.header $(PHLASH_BASE_NAME).bi4.header $(PHLASH_BASE_NAME).bi5.header $(PHLASH_BASE_NAME).bi6.header $(PHLASH_BASE_NAME).bi7.header $(PHLASH_BASE_NAME).bi8.header $(PHLASH_BASE_NAME).bi9.header $(PHLASH_BASE_NAME).bia.header $(PHLASH_BASE_NAME).bio.header ; + +makerule $(PHLASH_BASE_NAME).bi1.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi1 ; dd if=$< of=$@ bs=1 count=160 +makerule $(PHLASH_BASE_NAME).bi2.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi2 ; dd if=$< of=$@ bs=1 count=160 +makerule $(PHLASH_BASE_NAME).bi3.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi3 ; dd if=$< of=$@ bs=1 count=160 +makerule $(PHLASH_BASE_NAME).bi4.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi4 ; dd if=$< of=$@ bs=1 count=160 +makerule $(PHLASH_BASE_NAME).bi5.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi5 ; dd if=$< of=$@ bs=1 count=160 +makerule $(PHLASH_BASE_NAME).bi6.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi6 ; dd if=$< of=$@ bs=1 count=160 +makerule $(PHLASH_BASE_NAME).bi7.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi7 ; dd if=$< of=$@ bs=1 count=160 +makerule $(PHLASH_BASE_NAME).bi8.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi8 ; dd if=$< of=$@ bs=1 count=160 +makerule $(PHLASH_BASE_NAME).bi9.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi9 ; dd if=$< of=$@ bs=1 count=160 +makerule $(PHLASH_BASE_NAME).bia.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bia ; dd if=$< of=$@ bs=1 count=160 +makerule $(PHLASH_BASE_NAME).bio.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bio ; dd if=$< of=$@ bs=1 count=160 + +addaction clean rm -f $(PHLASH_BASE_NAME)* xa? diff --git a/src/mainboard/dell/350/ipl_3com905.S b/src/mainboard/dell/350/ipl_3com905.S new file mode 100644 index 0000000000..ca950f8e96 --- /dev/null +++ b/src/mainboard/dell/350/ipl_3com905.S @@ -0,0 +1,216 @@ +/* + * ipl.S: Initial Program Loader (IPL) for SiS 630 and M-System DoC Millennium + * + * + * Copyright 2000 Silicon Integrated Systems Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + * + * Reference: + * 1. SiS 630 Specification + * 2. System Management Bus Specification Rev 1.1 + * 3. PC SDRAM Serial Presence Detect (SPD) Specification Rev 1.2B + * 4. Booting From the DiskOnChip Millennium, M-Systems Application Note Ap-DOC-044 + * APR-2000, 93-SR-001-44-7L REV. 1.0 + * + * $Id$ + */ + +#include "ipl.h" + +.code16 +.org 0xfe00 + +dell350_3com905_start: + cli # Disables the maskable + # hardware interrupts. + + movw %cs, %ax # makes data segment == + movw %ax, %ds # code segment + + # move the eip to eax, then mask off the bits, + # so we have an address for the docipl. This address is used + # to diddle the docipl so we can read blocks. + + # enable writes on the docipl. + +init_complete: +sis630ipl_start: + /* O.K. we have DRAM now, so set up STACK for CALL/RET */ + movw $DOC_STACK_SEG, %ax + movw %ax, %ss + movw $SPL_RAM_SEG, %ax + movw %ax, %es +#ifdef STD_FLASH + movw $0xf000, %ax + movw %ax, %ds + xorw %sp, %sp # clear %sp + xorw %si, %si + xorw %di, %di + movw $0xffff, %cx + rep + movsb + + movw $DOC_WIN_SEG, %ax + movw %ax, %ds + +#else + movw $sis950_init_table, %si # unlock SiS 950 LPC + movw $0x05, %cx # select Clock Selection + movw $0x2e, %dx # and Flash ROM I/F + rep + outsb + movb $0xfd, %al # enable write, CLKIN = 24 MHZ + outb %al, $0x2f + + xorw %sp, %sp # clear %sp + xorw %dx, %dx # clear %dx, start of RAM + movw $0x800, %si # point %si to CDSN Data area + movw $0x1000, %di # point %di to CDSN Control area + movw $DOC_SPL_START_BLK, %bp # start page of LinuxBIOS + + movb $0x84, %al # Reset DOC Millennium + call doc_reset + + movb $0x85, %al # Turn into Normal Mode + call doc_reset + +read_next_page: + movw $0x1000, %di # point %di to CDSN Control area + +flash_command: + movb $0x03, 0x04(%di) # start command cycle + movb $0x00, (%si) # issue flash command Read00 + call doc_cycle_end + + movw %bp, %bx # %bp is current page number + +flash_address: + shll $0x08, %ebx + movb $0x03, %cl # this one is DANGEROUS but I am + # sure the upper 3 bytes == 0x00 + + movb $0x05, 0x04(%di) # start address cycle +0: + movb %bl, (%si) # write address to CDSNIO + shrw $0x08, %bx # shift next address byte + loop 0b + + call doc_cycle_end + +wait_for_flash_ready: + /* delay by reding NOP register before polling the FLASH READY bit, + this is inlined to save a call/ret pair */ +doc_delay: + movb $0x04, %cl # this one is DANGEROUS but I am + # sure the upper 3 bytes == 0x00 +0: + movb 0x20(%di), %al # read DOC NOP retisger + loop 0b # four times + + testb $0x80, 0x04(%di) # is flash ready ? + jz wait_for_flash_ready + + movb 0x1d(%di), %al # init read pipeline + movw $0x100, %cx # 1 page = 512 bytes + movw $0x800, %si # point %si to CDSN Data area + movw %dx, %di # restore saved current destination + rep + movsw + + movw %di, %dx # save current destination + incw %bp # increse current page number + cmpw $128, %bp # moved 63 KB ?? + jl read_next_page # no, read next page +#endif /*else STD_FLASH */ + +sis630ipl_end: + jmp spl_vector # jump to SPL vector + +/* ------------------------------------------------------------------------------------------*/ + +write_lpc_register: + /* Input: AH - register number. AL - register value. */ + movl $LPC_BRIDGE_BASE_ADDR, %edx + jmp write_common + +write_pci_register: + /* Input: AH - register number. AL - register value. */ + movl $NORTH_BRIDGE_BASE_ADDR, %edx + +write_common: + movw %ax, %cx # Save %ax to %cx. + + movzbl %ch, %eax # add register address to + addl %edx, %eax # PCI base address + + movw $PCI_COMMAND_PORT, %dx + outl %eax, %dx + + movw $PCI_DATA_PORT, %dx + andb $0x03, %al + addb %al, %dl + movb %cl, %al + outb %al, %dx + RET_SP # End of write_[lpc|pci]_reg + +read_spd: + /* Input: AH = 05h, AL = byte number of SPD to be read. + Output: BL = The value of specified SPD byte. */ + movb $0x05, %ah + CALL_BP(sis_set_smbus) + + movw $0x0312, %ax # Start, R/W byte Data + CALL_BP(sis_set_smbus) + +wait_for_smbus_read: + movb $0x80, %dl # Read SMBus status + inb %dx, %al + + testb $0x02, %al # if device errors + jnz read_spd_fail # then skip read SPD + + testb $0x08, %al # if not complete + jz wait_for_smbus_read # then wait SPD data complete + +read_spd_fail: + movb $0x08, %ah + +doc_reset: + /* Input: AL = value write to DOC_CONTROL register + Clobberd: CX */ + movb %al, 0x02(%di) # write DoC Control retister + movb %al, 0x02(%di) # twice + ret # End of doc_reset + +doc_cycle_end: + movb $0x00, 0x1e(%di) # flush write pepeline + movb $0x01, 0x04(%di) # end command cycle + ret + +reset_vector: +# .byte 0xea # jmp to fe00:0000, where IPL +# .word 0x0000, DOC_WIN_SEG # starts in DoC + + .byte 0xea # jmp to fe00:0000, where IPL + .word 0xfe00, 0xf000 # starts in DoC + +spl_vector: + .byte 0xea # jmp to 8000:0000, where SPL + .word 0x0000, SPL_RAM_SEG # (LinuxBIOS) starts in RAM + +end: + hlt diff --git a/src/mainboard/dell/350/mainboard.c b/src/mainboard/dell/350/mainboard.c new file mode 100644 index 0000000000..84a0d4ca66 --- /dev/null +++ b/src/mainboard/dell/350/mainboard.c @@ -0,0 +1,20 @@ +#include + +void +mainboard_fixup(void) +{ +} + +void +final_mainboard_fixup(void) +{ + void final_southbridge_fixup(void); + void final_superio_fixup(void); + + printk(KERN_INFO "DELL 350\n"); + + final_southbridge_fixup(); +#ifndef USE_NEW_SUPERIO_INTERFACE + final_superio_fixup(); +#endif +}