From bd2c7443f300b81811308d48a0a8fcb28c374f3a Mon Sep 17 00:00:00 2001 From: Cliff Huang Date: Sun, 1 Mar 2026 00:23:03 -0800 Subject: [PATCH] soc/intel/ptl: Add ISCLK for controlling PCIe clock source MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add two functions for disabling/enabling PCIe clocks to devices connected to root ports. These functions are used during device power sequencing at boot to ensure clocks are not driven to devices when their power is off. This prevents potential issues with PCIe link training and ensures proper power-on sequencing for connected devices. BUG=none TEST=Build and boot Panther Lake platform. Verify PCIe devices enumerate correctly and clock management functions properly during power sequences Signed-off-by: Cliff Huang Change-Id: I63f8e331b6ab18172fa32ff5c1539c71823aa247 Reviewed-on: https://review.coreboot.org/c/coreboot/+/91550 Reviewed-by: Jérémy Compostella Tested-by: build bot (Jenkins) --- src/soc/intel/pantherlake/Makefile.mk | 1 + src/soc/intel/pantherlake/include/soc/isclk.h | 14 +++++++++++++ src/soc/intel/pantherlake/isclk.c | 20 +++++++++++++++++++ 3 files changed, 35 insertions(+) create mode 100644 src/soc/intel/pantherlake/include/soc/isclk.h create mode 100644 src/soc/intel/pantherlake/isclk.c diff --git a/src/soc/intel/pantherlake/Makefile.mk b/src/soc/intel/pantherlake/Makefile.mk index b7ea31b1f6..24ef2e9d27 100644 --- a/src/soc/intel/pantherlake/Makefile.mk +++ b/src/soc/intel/pantherlake/Makefile.mk @@ -8,6 +8,7 @@ subdirs-y += ../../../cpu/intel/turbo # all (bootblock, verstage, romstage, postcar, ramstage) all-y += gpio.c +all-y += isclk.c bootblock-y += bootblock/bootblock.c bootblock-y += bootblock/pcd.c diff --git a/src/soc/intel/pantherlake/include/soc/isclk.h b/src/soc/intel/pantherlake/include/soc/isclk.h new file mode 100644 index 0000000000..dfa072eb5a --- /dev/null +++ b/src/soc/intel/pantherlake/include/soc/isclk.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef _SOC_PANTHERLAKE_ISCLK_H_ +#define _SOC_PANTHERLAKE_ISCLK_H_ + +#include + +/* Disable PCIe clock source; clock_number: 0-based */ +void soc_disable_pcie_clock_out(size_t clock_number); + +/* Enable PCIe clock source; clock_number: 0-based */ +void soc_enable_pcie_clock_out(size_t clock_number); + +#endif /* _SOC_PANTHERLAKE_ISCLK_H_ */ diff --git a/src/soc/intel/pantherlake/isclk.c b/src/soc/intel/pantherlake/isclk.c new file mode 100644 index 0000000000..649dcc843b --- /dev/null +++ b/src/soc/intel/pantherlake/isclk.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include + +#define ISCLK_PCR_BIOS_BUFFEN_H 0x8080 + +/* Disable PCIe clock source; clock_number: 0-based */ +void soc_disable_pcie_clock_out(size_t clock_number) +{ + pcr_rmw32(PID_ISCLK, ISCLK_PCR_BIOS_BUFFEN_H, ~BIT(clock_number), 0); +} + +/* Enable PCIe clock source; clock_number: 0-based */ +void soc_enable_pcie_clock_out(size_t clock_number) +{ + pcr_or32(PID_ISCLK, ISCLK_PCR_BIOS_BUFFEN_H, BIT(clock_number)); +}