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exynos5420: get rid of old exynos5420_config_l2_cache()

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We set up L2 cache early in romstage now so the old
function is now redundant.

Signed-off-by: David Hendricks <dhendrix@chromium.org>
BUG=none
BRANCH=none
TEST=built and booted on pit, cat /proc/cmdline shows 4 A15 cores

Change-Id: Icec93810ddd7feb48286d4b600cb2d58af38b7ef
Reviewed-on: https://gerrit.chromium.org/gerrit/65428
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
This commit is contained in:
David Hendricks 2013-08-09 18:19:29 -07:00 • committed by ChromeBot
commit bb91f1078e
5 changed files with 4 additions and 34 deletions
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30
src/cpu/samsung/exynos5420/cpu.c
View file

@ -185,33 +185,3 @@ struct chip_operations cpu_samsung_exynos5420_ops = {
CHIP_NAME("CPU Samsung Exynos 5420")
.enable_dev = enable_exynos5420_dev,
};
void exynos5420_config_l2_cache(void)
{
uint32_t val;
/*
* Bit 9 - L2 tag RAM setup (1 cycle)
* Bits 8:6 - L2 tag RAM latency (3 cycles)
* Bit 5 - L2 data RAM setup (1 cycle)
* Bits 2:0 - L2 data RAM latency (3 cycles)
*/
val = (1 << 9) | (0x2 << 6) | (1 << 5) | (0x2);
write_l2ctlr(val);
val = read_l2actlr();
/* L2ACTLR[3]: Disable clean/evict push to external */
val |= (1 << 3);
/* L2ACTLR[7]: Enable hazard detect timeout for A15 */
val |= (1 << 7);
/* L2ACTLR[27]: Prevents stopping the L2 logic clock */
val |= (1 << 27);
write_l2actlr(val);
/* Read the l2 control register to force things to take effect? */
val = read_l2ctlr();
}

1
src/cpu/samsung/exynos5420/cpu.h
View file

@ -263,7 +263,6 @@ static inline u32 get_fb_base_kb(void)
}
/* Procedures to setup Exynos5420 CPU */
void exynos5420_config_l2_cache(void);
void exynos5420_config_smp(void);
#endif /* _EXYNOS5420_CPU_H */

5
src/cpu/samsung/exynos5420/smp.c
View file

@ -271,7 +271,10 @@ static void power_down_core(void)
/* Configures the CPU states shard memory page and then shutdown all cores. */
static void configure_secondary_cores(void)
{
configure_l2ctlr();
if (get_bits(read_midr(), 4, 12) == PART_NUMBER_CORTEX_A15) {
configure_l2ctlr();
configure_l2actlr();
}
/* Currently we use power_down_core as callback for each core to
* shutdown itself, but it is also ok to directly set ARM_CORE*_CONFIG

1
src/mainboard/google/kirby/mainboard.c
View file

@ -325,7 +325,6 @@ static void mainboard_enable(device_t dev)
/* set up dcache and MMU */
/* FIXME: this should happen via resource allocator */
exynos5420_config_l2_cache();
mmu_init();
mmu_config_range(0, DRAM_START, DCACHE_OFF);
mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK);

1
src/mainboard/google/pit/mainboard.c
View file

@ -444,7 +444,6 @@ static void mainboard_enable(device_t dev)
/* set up dcache and MMU */
/* FIXME: this should happen via resource allocator */
exynos5420_config_l2_cache();
mmu_init();
mmu_config_range(0, DRAM_START, DCACHE_OFF);
mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK);