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UPSTREAM: intel cache_as_ram: Fix typo in comment

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Change-Id: I2539e490e160e01cab2ad8d2086d2f242a88c640
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/15223
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
(cherry-picked from commit 9d2762ca6f)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/354184
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
This commit is contained in:
Kyösti Mälkki 2016-06-17 07:54:36 +03:00 • committed by chrome-bot
commit b979b55040
3 changed files with 3 additions and 3 deletions
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2
src/cpu/intel/haswell/cache_as_ram.inc
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@ -236,7 +236,7 @@ before_romstage:
post_code(0x38)
/* Setup stack as indicated by return value from ramstage_main(). */
/* Setup stack as indicated by return value from romstage_main(). */
movl %ebx, %esp
/* Get number of MTRRs. */

2
src/soc/intel/baytrail/romstage/cache_as_ram.inc
View file

@ -217,7 +217,7 @@ before_romstage:
post_code(0x2e)
/* Setup stack as indicated by return value from ramstage_main(). */
/* Setup stack as indicated by return value from romstage_main(). */
movl %ebx, %esp
/* Get number of MTRRs. */

2
src/soc/intel/broadwell/romstage/cache_as_ram.inc
View file

@ -256,7 +256,7 @@ before_romstage:
post_code(0x38)
/* Setup stack as indicated by return value from ramstage_main(). */
/* Setup stack as indicated by return value from romstage_main(). */
movl %ebx, %esp
/* Get number of MTRRs. */