From b979b5504004600455293a82c627327976005397 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Fri, 17 Jun 2016 07:54:36 +0300 Subject: [PATCH] UPSTREAM: intel cache_as_ram: Fix typo in comment Change-Id: I2539e490e160e01cab2ad8d2086d2f242a88c640 Original-Signed-off-by: Kysti Mlkki Original-Reviewed-on: https://review.coreboot.org/15223 Original-Reviewed-by: Aaron Durbin Original-Reviewed-by: Paul Menzel (cherry-picked from commit 9d2762ca6f2c0414afdca210ba996db7a0956690) Signed-off-by: Martin Roth Reviewed-on: https://chromium-review.googlesource.com/354184 Commit-Ready: Furquan Shaikh Tested-by: Furquan Shaikh Reviewed-by: Furquan Shaikh --- src/cpu/intel/haswell/cache_as_ram.inc | 2 +- src/soc/intel/baytrail/romstage/cache_as_ram.inc | 2 +- src/soc/intel/broadwell/romstage/cache_as_ram.inc | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/cpu/intel/haswell/cache_as_ram.inc b/src/cpu/intel/haswell/cache_as_ram.inc index e09e74b6c2..2ccef786fa 100644 --- a/src/cpu/intel/haswell/cache_as_ram.inc +++ b/src/cpu/intel/haswell/cache_as_ram.inc @@ -236,7 +236,7 @@ before_romstage: post_code(0x38) - /* Setup stack as indicated by return value from ramstage_main(). */ + /* Setup stack as indicated by return value from romstage_main(). */ movl %ebx, %esp /* Get number of MTRRs. */ diff --git a/src/soc/intel/baytrail/romstage/cache_as_ram.inc b/src/soc/intel/baytrail/romstage/cache_as_ram.inc index 4a1d31f6da..dcb62960f9 100644 --- a/src/soc/intel/baytrail/romstage/cache_as_ram.inc +++ b/src/soc/intel/baytrail/romstage/cache_as_ram.inc @@ -217,7 +217,7 @@ before_romstage: post_code(0x2e) - /* Setup stack as indicated by return value from ramstage_main(). */ + /* Setup stack as indicated by return value from romstage_main(). */ movl %ebx, %esp /* Get number of MTRRs. */ diff --git a/src/soc/intel/broadwell/romstage/cache_as_ram.inc b/src/soc/intel/broadwell/romstage/cache_as_ram.inc index a636e9f7ad..20ef6e9758 100644 --- a/src/soc/intel/broadwell/romstage/cache_as_ram.inc +++ b/src/soc/intel/broadwell/romstage/cache_as_ram.inc @@ -256,7 +256,7 @@ before_romstage: post_code(0x38) - /* Setup stack as indicated by return value from ramstage_main(). */ + /* Setup stack as indicated by return value from romstage_main(). */ movl %ebx, %esp /* Get number of MTRRs. */