From b9759ba5500562c218fa4160821b3eea87c2b441 Mon Sep 17 00:00:00 2001 From: David Wu Date: Mon, 10 Mar 2025 10:03:11 +0800 Subject: [PATCH] mb/google/nissa/var/riven: Modify eMMC DLL tuning value Riven cannot boot into OS from 2nd source eMMC, show message "Something went wrong booting from internal disk" and stop in depthcharge. According to Intel provides eMMC DLL delay patch that tuning on each riven different eMMC system to modify eMMC DLL tuning value to improve initialization reliability. BUG=b:401663746 TEST=Cold reboot stress test over 2500 cycles Change-Id: Ib36650f2a8fca486c8c89fb9f2ef42452b7a4cfa Signed-off-by: David Wu Reviewed-on: https://review.coreboot.org/c/coreboot/+/86778 Reviewed-by: Eric Lai Reviewed-by: Simon Yang Tested-by: build bot (Jenkins) --- src/mainboard/google/brya/variants/riven/overridetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/brya/variants/riven/overridetree.cb b/src/mainboard/google/brya/variants/riven/overridetree.cb index 9e5fa3cd2e..1cb63134db 100644 --- a/src/mainboard/google/brya/variants/riven/overridetree.cb +++ b/src/mainboard/google/brya/variants/riven/overridetree.cb @@ -62,7 +62,7 @@ chip soc/intel/alderlake # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119. # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119. - register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C1B4F3C" + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C1B4F1B" # EMMC RX CMD/DATA Delay 2 # Refer to EDS-Vol2-42.3.12.