UPSTREAM: soc/intel/skylake: Add option to disable host reads to PMC XRAM

FSP disables host access to shadowed PMC XRAM registers by default,
it also provides a UPD to enable/disable host reads to these regiters.
Expose the same in devicetree as a config option.

BUG=none
BRANCH=none
TEST=none

Change-Id: I1ffd08c2aa4abb52787ae7b8c91cbc734290f6ec
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ffe58107df
Original-Change-Id: Iaa33aa3233bda4f050da37d1d8af0556311c9496
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18319
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/458355

src/soc/intel/skylake/chip.h

@@ -402,6 +402,9 @@ struct soc_intel_skylake_config {
 	 */
 	u32 PrmrrSize;
 
+	/* Enable/Disable host reads to PMC XRAM registers */
+	u8 PchPmPmcReadDisable;
+
 	/* Statically clock gate 8254 PIT. */
 	u8 clock_gate_8254;
 

src/soc/intel/skylake/chip_fsp20.c

@@ -258,6 +258,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 	params->FastPkgCRampDisableGt = config->FastPkgCRampDisableGt;
 	params->FastPkgCRampDisableSa = config->FastPkgCRampDisableSa;
 
+	/* Enable PMC XRAM read */
+	tconfig->PchPmPmcReadDisable = config->PchPmPmcReadDisable;
+
 	soc_irq_settings(params);
 }