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UPSTREAM: soc/intel/skylake: Add configs for enabling DCI and TraceHub

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Add configs for enabling Intel TraceHub and DCI for aid in debugging.

BUG=none
BRANCH=none
TEST=none

Change-Id: Ia9422733d4b85614774614ccf6af8b525d0ca401
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6375512896
Original-Change-Id: Ic40f9499c0125070049856e242e89024ca5a1c4e
Original-Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18791
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/458354
This commit is contained in:
Aamir Bohra 2017-02-06 21:48:48 +05:30 • committed by chrome-bot
commit 3cef1a9f63
2 changed files with 19 additions and 8 deletions
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5
src/soc/intel/skylake/chip.h
View file

@ -157,6 +157,11 @@ struct soc_intel_skylake_config {
/* Trace Hub function */
u8 EnableTraceHub;
u32 TraceHubMemReg0Size;
u32 TraceHubMemReg1Size;
/* DCI Enable/Disable */
u8 PchDciEn;
/* Pcie Root Ports */
u8 PcieRpEnable[CONFIG_MAX_ROOT_PORTS];

22
src/soc/intel/skylake/romstage/romstage_fsp20.c
View file

@ -185,16 +185,12 @@ static void cpu_flex_override(FSP_M_CONFIG *m_cfg)
m_cfg->CpuRatio = (flex_ratio.lo >> 8) & 0xff;
}
static void soc_memory_init_params(FSP_M_CONFIG *m_cfg)
static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
const struct soc_intel_skylake_config *config)
{
const struct device *dev;
const struct soc_intel_skylake_config *config;
int i;
uint32_t mask = 0;
/* Set the parameters for MemoryInit */
dev = dev_find_slot(0, PCI_DEVFN(PCH_DEV_SLOT_LPC, 0));
config = dev->chip_info;
/*
* Set IGD stolen size to 64MB. The FBC hardware for skylake does not
* have access to the bios_reserved range so it always assumes 8MB is
@ -207,7 +203,6 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg)
m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE;
m_cfg->IedSize = CONFIG_IED_REGION_SIZE;
m_cfg->ProbelessTrace = config->ProbelessTrace;
m_cfg->EnableTraceHub = config->EnableTraceHub;
if (vboot_recovery_mode_enabled())
m_cfg->SaGv = 0; /* Disable SaGv in recovery mode. */
else
@ -228,10 +223,15 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg)
void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
{
const struct device *dev;
const struct soc_intel_skylake_config *config;
FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
FSP_M_TEST_CONFIG *m_t_cfg = &mupd->FspmTestConfig;
soc_memory_init_params(m_cfg);
dev = dev_find_slot(0, PCI_DEVFN(PCH_DEV_SLOT_LPC, 0));
config = dev->chip_info;
soc_memory_init_params(m_cfg, config);
/* Enable DMI Virtual Channel for ME */
m_t_cfg->DmiVcm = 0x01;
@ -240,6 +240,12 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
m_t_cfg->SendDidMsg = 0x01;
m_t_cfg->DidInitStat = 0x01;
/* DCI and TraceHub configs */
m_t_cfg->PchDciEn = config->PchDciEn;
m_cfg->EnableTraceHub = config->EnableTraceHub;
m_cfg->TraceHubMemReg0Size = config->TraceHubMemReg0Size;
m_cfg->TraceHubMemReg1Size = config->TraceHubMemReg1Size;
mainboard_memory_init_params(mupd);
}