From b375a5bbba0d8c252b8d44c387e5b7d349121fbd Mon Sep 17 00:00:00 2001 From: Ivy Jian Date: Mon, 14 Apr 2025 11:03:08 +0800 Subject: [PATCH] mb/google/nissa/var/dirks: correct usb2_ports setting When re-purposing the TCSS port to USB Type-A, PortResetMessageEnable must be enabled for USB2 ports that are paired with the CPU XHCI port. Set to USB2_PORT_TYPE_C to enable PortResetMessageEnable. Also remove the workaround. (workaround CL:87053) BUG=b:400809281 TEST=Connecting a USB3 speed device,using lsusb -t to check enumerated status. with change: /: Bus 02.Port 1: Dev 1, Class=root_hub, Driver=xhci_hcd/2p, 20000M/x2 |__ Port 2: Dev 2, If 0, Class=Mass Storage, Driver=usb-storage, 5000M without change: /: Bus 03.Port 1: Dev 1, Class=root_hub, Driver=xhci_hcd/12p, 480M |__ Port 2: Dev 4, If 0, Class=Mass Storage, Driver=usb-storage, 480M Change-Id: I7c4743d1d3bcf2567fdca9c0e07ed02c240d4baf Signed-off-by: Ivy Jian Reviewed-on: https://review.coreboot.org/c/coreboot/+/87301 Reviewed-by: Eric Lai Tested-by: build bot (Jenkins) Reviewed-by: Kapil Porwal --- src/mainboard/google/brya/Kconfig | 4 ---- src/mainboard/google/brya/variants/dirks/overridetree.cb | 4 +++- 2 files changed, 3 insertions(+), 5 deletions(-) diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index b2efed7ad9..931cef4218 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -1183,8 +1183,4 @@ config SKIP_RAM_ID_STRAPS If unsure, leave this option disabled. -config D3COLD_SUPPORT - bool - default n if BOARD_GOOGLE_DIRKS - endif # BOARD_GOOGLE_BRYA_COMMON diff --git a/src/mainboard/google/brya/variants/dirks/overridetree.cb b/src/mainboard/google/brya/variants/dirks/overridetree.cb index d80ddc488c..6a5d444f12 100644 --- a/src/mainboard/google/brya/variants/dirks/overridetree.cb +++ b/src/mainboard/google/brya/variants/dirks/overridetree.cb @@ -71,7 +71,9 @@ chip soc/intel/alderlake register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_A21, .pad_auxn_dc = GPP_A22}" register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C0 - register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # USB2_A0 + # This port is repurposed from Type-C to type-A port. + # Still declare it as Type-C port in order to set PortResetMessageEnable UPD. + register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC0)" # USB2_A0 register "usb2_ports[2]" = "USB2_PORT_MID(OC1)" # USB2_A1 register "usb2_ports[3]" = "USB2_PORT_MID(OC2)" # USB2_A2 register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" # USB2_A3