From b322d309442c0ae11e407a1a1727cefdbdc205cd Mon Sep 17 00:00:00 2001 From: David Wu Date: Mon, 9 Jun 2025 09:28:20 +0800 Subject: [PATCH] mb/google/brya/var/moxie: Enable RTD3 for SSD to resolve S0ix issue Some SSDs block the CPU from reaching C10 during the S0ix suspend without the RTD3 configuration. Add PCIe RTD3 support so NVMe gets placed into D3 state when entering S0ix. Enable and reset GPIOs are configured as per pin mapping in gpio.c. BUG=b:391612392 b:421064225 TEST=Run suspend_stress_test on moxie and verify that the device suspends to S0ix. Change-Id: I6b2c264fd7244ab84e82919354afb2b49a22177a Signed-off-by: David Wu Reviewed-on: https://review.coreboot.org/c/coreboot/+/88000 Reviewed-by: Subrata Banik Tested-by: build bot (Jenkins) Reviewed-by: Eric Lai Reviewed-by: Pranava Y N --- src/mainboard/google/brya/variants/moxie/overridetree.cb | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/mainboard/google/brya/variants/moxie/overridetree.cb b/src/mainboard/google/brya/variants/moxie/overridetree.cb index 19a20a14ec..9733305b69 100644 --- a/src/mainboard/google/brya/variants/moxie/overridetree.cb +++ b/src/mainboard/google/brya/variants/moxie/overridetree.cb @@ -148,6 +148,13 @@ chip soc/intel/alderlake .clk_src = 0, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" + chip soc/intel/common/block/pcie/rtd3 + register "is_storage" = "true" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F14)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)" + register "srcclk_pin" = "0" + device generic 0 on end + end end device ref tbt_pcie_rp0 on probe MB_USBC TC_USB4