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UPSTREAM: soc/baytrail: add missing USB port defs

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Add device/address stub for XHCI USB port 7.
Stub data will be supplemented by board-specific info
added in subsequent commits.

BUG=none
BRANCH=none
TEST=none

Change-Id: Ifd6dec3603caf24ab9214b35253845ea38446421
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f9c46f0ebc
Original-Change-Id: Iae874a9ba01e9428e07cf7ff15e663365b2354a9
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19972
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/523966
This commit is contained in:
Matt DeVillier 2017-04-17 18:45:55 -05:00 • committed by chrome-bot
commit b2371f134d
1 changed files with 1 additions and 0 deletions
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src/soc/intel/baytrail/acpi/xhci.asl
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@ -27,5 +27,6 @@ Device (XHCI)
Device (PRT2) { Name (_ADR, 2) }
Device (PRT3) { Name (_ADR, 3) }
Device (PRT4) { Name (_ADR, 4) }
Device (SSP1) { Name (_ADR, 7) }
}
}