From b20f6d27e21b3b4b94ef655fb4761047a37d2c7e Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Mon, 21 Jul 2025 14:17:50 -0500 Subject: [PATCH] device/dram: Rename 'USE_DDRx' config options Rename config options 'USE_DDRx' to 'DRAM_SUPPORT_DDRx' to make them less clunky, and in preparation to expand their use inside SoC code. Change-Id: Ie6edd730c5cbad679a90fcf7989a942d9b2dd3d8 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/88520 Tested-by: build bot (Jenkins) Reviewed-by: Reviewed-by: Angel Pons --- src/device/dram/Kconfig | 20 +++++++++---------- src/device/dram/Makefile.mk | 22 ++++++++++----------- src/mainboard/hardkernel/odroid-h4/Kconfig | 2 +- src/mainboard/protectli/vault_adl_p/Kconfig | 2 +- src/northbridge/amd/pi/00730F01/Kconfig | 2 +- src/northbridge/intel/gm45/Kconfig | 4 ++-- src/northbridge/intel/haswell/Kconfig | 2 +- src/northbridge/intel/i945/Kconfig | 2 +- src/northbridge/intel/ironlake/Kconfig | 2 +- src/northbridge/intel/pineview/Kconfig | 4 ++-- src/northbridge/intel/sandybridge/Kconfig | 2 +- src/northbridge/intel/x4x/Kconfig | 4 ++-- src/soc/amd/cezanne/Kconfig | 4 ++-- src/soc/amd/common/fsp/dmi.c | 6 +++--- src/soc/amd/glinda/Kconfig | 2 +- src/soc/amd/mendocino/Kconfig | 2 +- src/soc/amd/phoenix/Kconfig | 2 +- src/soc/amd/picasso/Kconfig | 2 +- src/soc/amd/stoneyridge/Kconfig | 2 +- src/soc/intel/baytrail/Kconfig | 2 +- src/soc/intel/snowridge/Kconfig | 2 +- 21 files changed, 46 insertions(+), 46 deletions(-) diff --git a/src/device/dram/Kconfig b/src/device/dram/Kconfig index b9b5de4f6d..ceb5be4caf 100644 --- a/src/device/dram/Kconfig +++ b/src/device/dram/Kconfig @@ -1,31 +1,31 @@ ## SPDX-License-Identifier: GPL-2.0-only -config USE_DDR5 +config DRAM_SUPPORT_DDR5 bool default n help - system supports DDR5 memory + System supports DDR5 memory -config USE_LPDDR4 +config DRAM_SUPPORT_LPDDR4 bool default n help - system supports LPDDR4 memory + System supports LPDDR4 memory -config USE_DDR4 +config DRAM_SUPPORT_DDR4 bool default n help - system supports DDR4 memory + System supports DDR4 memory -config USE_DDR3 +config DRAM_SUPPORT_DDR3 bool default n help - system supports DDR3 memory + System supports DDR3 memory -config USE_DDR2 +config DRAM_SUPPORT_DDR2 bool default n help - system supports DDR2 memory + System supports DDR2 memory diff --git a/src/device/dram/Makefile.mk b/src/device/dram/Makefile.mk index 7772db2de5..74ef7a054c 100644 --- a/src/device/dram/Makefile.mk +++ b/src/device/dram/Makefile.mk @@ -4,18 +4,18 @@ romstage-y += ddr_common.c ramstage-y += ddr_common.c ramstage-y += spd.c -romstage-$(CONFIG_USE_DDR5) += ddr5.c -ramstage-$(CONFIG_USE_DDR5) += ddr5.c +romstage-$(CONFIG_DRAM_SUPPORT_DDR5) += ddr5.c +ramstage-$(CONFIG_DRAM_SUPPORT_DDR5) += ddr5.c -romstage-$(CONFIG_USE_LPDDR4) += lpddr4.c -ramstage-$(CONFIG_USE_LPDDR4) += lpddr4.c +romstage-$(CONFIG_DRAM_SUPPORT_LPDDR4) += lpddr4.c +ramstage-$(CONFIG_DRAM_SUPPORT_LPDDR4) += lpddr4.c -romstage-$(CONFIG_USE_DDR4) += ddr4.c -romstage-$(CONFIG_USE_DDR4) += rcd.c -ramstage-$(CONFIG_USE_DDR4) += ddr4.c +romstage-$(CONFIG_DRAM_SUPPORT_DDR4) += ddr4.c +romstage-$(CONFIG_DRAM_SUPPORT_DDR4) += rcd.c +ramstage-$(CONFIG_DRAM_SUPPORT_DDR4) += ddr4.c -romstage-$(CONFIG_USE_DDR3) += ddr3.c -ramstage-$(CONFIG_USE_DDR3) += ddr3.c +romstage-$(CONFIG_DRAM_SUPPORT_DDR3) += ddr3.c +ramstage-$(CONFIG_DRAM_SUPPORT_DDR3) += ddr3.c -romstage-$(CONFIG_USE_DDR2) += ddr2.c -ramstage-$(CONFIG_USE_DDR2) += ddr2.c +romstage-$(CONFIG_DRAM_SUPPORT_DDR2) += ddr2.c +ramstage-$(CONFIG_DRAM_SUPPORT_DDR2) += ddr2.c diff --git a/src/mainboard/hardkernel/odroid-h4/Kconfig b/src/mainboard/hardkernel/odroid-h4/Kconfig index 3e03116db7..146d245dc7 100644 --- a/src/mainboard/hardkernel/odroid-h4/Kconfig +++ b/src/mainboard/hardkernel/odroid-h4/Kconfig @@ -15,7 +15,7 @@ config BOARD_SPECIFIC_OPTIONS select SUPERIO_ITE_IT8613E select SOC_INTEL_ALDERLAKE_PCH_N select SOC_INTEL_COMMON_BLOCK_HDA_VERB - select USE_DDR5 + select DRAM_SUPPORT_DDR5 config MAINBOARD_DIR default "hardkernel/odroid-h4" diff --git a/src/mainboard/protectli/vault_adl_p/Kconfig b/src/mainboard/protectli/vault_adl_p/Kconfig index b7578ab91b..4cfea63cf2 100644 --- a/src/mainboard/protectli/vault_adl_p/Kconfig +++ b/src/mainboard/protectli/vault_adl_p/Kconfig @@ -15,7 +15,7 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_ACPI_TABLES select INTEL_GMA_HAVE_VBT select MEMORY_MAPPED_TPM - select USE_DDR5 + select DRAM_SUPPORT_DDR5 config MAINBOARD_DIR default "protectli/vault_adl_p" diff --git a/src/northbridge/amd/pi/00730F01/Kconfig b/src/northbridge/amd/pi/00730F01/Kconfig index 46acb2d59d..3c2829efe7 100644 --- a/src/northbridge/amd/pi/00730F01/Kconfig +++ b/src/northbridge/amd/pi/00730F01/Kconfig @@ -2,7 +2,7 @@ config NORTHBRIDGE_AMD_PI_00730F01 bool - select USE_DDR3 + select DRAM_SUPPORT_DDR3 if NORTHBRIDGE_AMD_PI_00730F01 diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig index fef0d735b3..a776217475 100644 --- a/src/northbridge/intel/gm45/Kconfig +++ b/src/northbridge/intel/gm45/Kconfig @@ -8,8 +8,8 @@ config NORTHBRIDGE_INTEL_GM45 select INTEL_GMA_ACPI select INTEL_GMA_SSC_ALTERNATE_REF select HAVE_X86_64_SUPPORT - select USE_DDR3 - select USE_DDR2 + select DRAM_SUPPORT_DDR3 + select DRAM_SUPPORT_DDR2 select NEED_SMALL_2MB_PAGE_TABLES if NORTHBRIDGE_INTEL_GM45 diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig index 6191cb6ccf..c57f1ec380 100644 --- a/src/northbridge/intel/haswell/Kconfig +++ b/src/northbridge/intel/haswell/Kconfig @@ -6,7 +6,7 @@ config NORTHBRIDGE_INTEL_HASWELL select CACHE_MRC_SETTINGS select INTEL_DDI select INTEL_GMA_ACPI - select USE_DDR3 + select DRAM_SUPPORT_DDR3 if NORTHBRIDGE_INTEL_HASWELL diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig index 32eff1a611..c4e17f90bf 100644 --- a/src/northbridge/intel/i945/Kconfig +++ b/src/northbridge/intel/i945/Kconfig @@ -8,7 +8,7 @@ config NORTHBRIDGE_INTEL_I945 select INTEL_GMA_SSC_ALTERNATE_REF select INTEL_EDID select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT - select USE_DDR2 + select DRAM_SUPPORT_DDR2 select NEED_SMALL_2MB_PAGE_TABLES if NORTHBRIDGE_INTEL_I945 diff --git a/src/northbridge/intel/ironlake/Kconfig b/src/northbridge/intel/ironlake/Kconfig index 2bafebf92e..39566a6e5f 100644 --- a/src/northbridge/intel/ironlake/Kconfig +++ b/src/northbridge/intel/ironlake/Kconfig @@ -8,7 +8,7 @@ config NORTHBRIDGE_INTEL_IRONLAKE select INTEL_GMA_ACPI select CACHE_MRC_SETTINGS select HAVE_DEBUG_RAM_SETUP - select USE_DDR3 + select DRAM_SUPPORT_DDR3 select NEED_SMALL_2MB_PAGE_TABLES if NORTHBRIDGE_INTEL_IRONLAKE diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig index 59cfcd5e0a..a05b866dad 100644 --- a/src/northbridge/intel/pineview/Kconfig +++ b/src/northbridge/intel/pineview/Kconfig @@ -8,8 +8,8 @@ config NORTHBRIDGE_INTEL_PINEVIEW select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT select INTEL_EDID if MAINBOARD_DO_NATIVE_VGA_INIT select INTEL_GMA_ACPI - select USE_DDR3 - select USE_DDR2 + select DRAM_SUPPORT_DDR3 + select DRAM_SUPPORT_DDR2 select NEED_SMALL_2MB_PAGE_TABLES if NORTHBRIDGE_INTEL_PINEVIEW diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index 973eed8bbd..9972a43da0 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -7,7 +7,7 @@ config NORTHBRIDGE_INTEL_SANDYBRIDGE select HAVE_DEBUG_RAM_SETUP select INTEL_GMA_ACPI select NEED_SMALL_2MB_PAGE_TABLES - select USE_DDR3 + select DRAM_SUPPORT_DDR3 if NORTHBRIDGE_INTEL_SANDYBRIDGE diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig index 097e11126c..6fa4551957 100644 --- a/src/northbridge/intel/x4x/Kconfig +++ b/src/northbridge/intel/x4x/Kconfig @@ -8,8 +8,8 @@ config NORTHBRIDGE_INTEL_X4X select CACHE_MRC_SETTINGS select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES select HAVE_X86_64_SUPPORT - select USE_DDR3 - select USE_DDR2 + select DRAM_SUPPORT_DDR3 + select DRAM_SUPPORT_DDR2 select NEED_SMALL_2MB_PAGE_TABLES if NORTHBRIDGE_INTEL_X4X diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 96e4f31e50..ebe96e40d9 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -80,8 +80,8 @@ config SOC_AMD_CEZANNE select SOC_AMD_COMMON_ROMSTAGE_LEGACY_DMA_FIXUP select SSE2 select UDK_2017_BINDING - select USE_DDR4 - select USE_LPDDR4 + select DRAM_SUPPORT_DDR4 + select DRAM_SUPPORT_LPDDR4 select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE diff --git a/src/soc/amd/common/fsp/dmi.c b/src/soc/amd/common/fsp/dmi.c index d132590483..f820e73139 100644 --- a/src/soc/amd/common/fsp/dmi.c +++ b/src/soc/amd/common/fsp/dmi.c @@ -23,11 +23,11 @@ */ static uint16_t ddr_speed_mhz_to_reported_mts(uint16_t ddr_type, uint16_t speed) { - if (CONFIG(USE_DDR4) && ddr_type == MEMORY_TYPE_DDR4) + if (CONFIG(DRAM_SUPPORT_DDR4) && ddr_type == MEMORY_TYPE_DDR4) return ddr4_speed_mhz_to_reported_mts(speed); - else if (CONFIG(USE_LPDDR4) && ddr_type == MEMORY_TYPE_LPDDR4) + else if (CONFIG(DRAM_SUPPORT_LPDDR4) && ddr_type == MEMORY_TYPE_LPDDR4) return lpddr4_speed_mhz_to_reported_mts(speed); - else if (CONFIG(USE_DDR5) && (ddr_type == MEMORY_TYPE_DDR5 || + else if (CONFIG(DRAM_SUPPORT_DDR5) && (ddr_type == MEMORY_TYPE_DDR5 || ddr_type == MEMORY_TYPE_LPDDR5)) return ddr5_speed_mhz_to_reported_mts(speed); diff --git a/src/soc/amd/glinda/Kconfig b/src/soc/amd/glinda/Kconfig index 868a984bcc..5cd7e7d1dc 100644 --- a/src/soc/amd/glinda/Kconfig +++ b/src/soc/amd/glinda/Kconfig @@ -84,7 +84,7 @@ config SOC_AMD_GLINDA select SOC_FILL_CPU_CACHE_INFO select SSE2 select UDK_2017_BINDING - select USE_DDR5 + select DRAM_SUPPORT_DDR5 select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE diff --git a/src/soc/amd/mendocino/Kconfig b/src/soc/amd/mendocino/Kconfig index 2adb012264..fcbc53b10c 100644 --- a/src/soc/amd/mendocino/Kconfig +++ b/src/soc/amd/mendocino/Kconfig @@ -86,7 +86,7 @@ config SOC_AMD_REMBRANDT_BASE select SOC_AMD_COMMON_ROMSTAGE_LEGACY_DMA_FIXUP select SSE2 select UDK_2017_BINDING - select USE_DDR5 + select DRAM_SUPPORT_DDR5 select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE diff --git a/src/soc/amd/phoenix/Kconfig b/src/soc/amd/phoenix/Kconfig index ac227b9f6f..5379baf7dd 100644 --- a/src/soc/amd/phoenix/Kconfig +++ b/src/soc/amd/phoenix/Kconfig @@ -73,7 +73,7 @@ config SOC_AMD_PHOENIX_BASE select SOC_AMD_COMMON_BLOCK_XHCI select SOC_AMD_COMMON_ROMSTAGE_LEGACY_DMA_FIXUP select SSE2 - select USE_DDR5 + select DRAM_SUPPORT_DDR5 select VBOOT_DEFINE_WIDEVINE_COUNTERS if VBOOT_STARTS_BEFORE_BOOTBLOCK select VBOOT_X86_SHA256_ACCELERATION if VBOOT select X86_AMD_FIXED_MTRRS diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 5678aaf1fb..f85d420697 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -70,7 +70,7 @@ config SOC_AMD_PICASSO select SOC_AMD_SUPPORTS_WARM_RESET select SSE2 select UDK_2017_BINDING - select USE_DDR4 + select DRAM_SUPPORT_DDR4 select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index 47de10290c..2abd9d7985 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -46,7 +46,7 @@ config SOC_AMD_STONEYRIDGE select SOC_AMD_COMMON_LATE_SMM_LOCKING select SSE2 select TSC_SYNC_LFENCE - select USE_DDR4 + select DRAM_SUPPORT_DDR4 select X86_AMD_FIXED_MTRRS help AMD support for SOCs in Family 15h Models 60h-6Fh and Models 70h-7Fh. diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 09fdbbaae4..1b7770241c 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -32,7 +32,7 @@ config SOC_INTEL_BAYTRAIL select CPU_INTEL_COMMON select CPU_HAS_L2_ENABLE_MSR select TCO_SPACE_NOT_YET_SPLIT - select USE_DDR3 + select DRAM_SUPPORT_DDR3 select NEED_SMALL_2MB_PAGE_TABLES help Bay Trail M/D part support. diff --git a/src/soc/intel/snowridge/Kconfig b/src/soc/intel/snowridge/Kconfig index ad77f9a1ea..afc2f40747 100644 --- a/src/soc/intel/snowridge/Kconfig +++ b/src/soc/intel/snowridge/Kconfig @@ -27,7 +27,7 @@ config SOC_INTEL_SNOWRIDGE select ACPI_INTEL_HARDWARE_SLEEP_VALUES ## Device - select USE_DDR4 + select DRAM_SUPPORT_DDR4 ## Drivers select CACHE_MRC_SETTINGS