diff --git a/src/Kconfig b/src/Kconfig
index 1c8e86ba25..10e424e100 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -996,6 +996,14 @@ config DEBUG_COVERAGE
 	  If enabled, the code coverage hooks in coreboot will output some
 	  information about the coverage data that is dumped.
 
+config BOARD_ID_SUPPORT
+	bool "Discover board ID and store it in coreboot table"
+	default n
+	help
+	  If enabled, coreboot discovers the board id of the hardware it is
+	  running on and reports it through the coreboot table to the rest of
+	  the system.
+
 config TERTIARY_BOARD_ID
 	bool "Interpret board ID GPIOs as tertiary inputs"
 	default n if ARCH_X86
diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h
index 356c163873..496c93c055 100644
--- a/src/include/boot/coreboot_tables.h
+++ b/src/include/boot/coreboot_tables.h
@@ -244,6 +244,14 @@ struct lb_x86_rom_mtrr {
 	uint32_t index;
 };
 
+#define LB_TAG_BOARD_ID		0x0025
+struct lb_board_id {
+	uint32_t tag;
+	uint32_t size;
+	/* Board ID as retrieved from the board revision GPIOs. */
+	uint32_t board_id;
+};
+
 /* The following structures are for the cmos definitions table */
 #define LB_TAG_CMOS_OPTION_TABLE 200
 /* cmos header record */
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 5cdbc19e7e..9d4c83e675 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -58,7 +58,6 @@ romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
 romstage-$(CONFIG_EARLY_CBMEM_INIT) += cbmem.c
 romstage-y += compute_ip_checksum.c
 romstage-$(CONFIG_ARCH_ROMSTAGE_X86_32) += gcc.c
-romstage-$(CONFIG_TERTIARY_BOARD_ID) += tristate_gpios.c
 
 ramstage-y += hardwaremain.c
 ramstage-y += selfboot.c
@@ -90,6 +89,7 @@ ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += edid.c
 ramstage-y += memrange.c
 ramstage-$(CONFIG_COOP_MULTITASKING) += thread.c
 ramstage-$(CONFIG_TIMER_QUEUE) += timer_queue.c
+ramstage--${CONFIG_TERTIARY_BOARD_ID} += tristate_gpios.c
 
 # The CBMEM implementations are chosen based on CONFIG_DYNAMIC_CBMEM.
 ifeq ($(CONFIG_DYNAMIC_CBMEM),y)
diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c
index cbec74e4d6..00777ad77b 100644
--- a/src/lib/coreboot_table.c
+++ b/src/lib/coreboot_table.c
@@ -25,6 +25,7 @@
 #include <boot/coreboot_tables.h>
 #include <string.h>
 #include <version.h>
+#include <boardid.h>
 #include <device/device.h>
 #include <stdlib.h>
 #include <cbfs.h>
@@ -217,9 +218,9 @@ static void lb_vbnv(struct lb_header *header)
 #endif
 }
 
-#if CONFIG_VBOOT_VERIFY_FIRMWARE || CONFIG_VBOOT2_VERIFY_FIRMWARE
 static void lb_vboot_handoff(struct lb_header *header)
 {
+#if CONFIG_VBOOT_VERIFY_FIRMWARE || CONFIG_VBOOT2_VERIFY_FIRMWARE
 	void *addr;
 	uint32_t size;
 	struct lb_range *vbho;
@@ -232,12 +233,23 @@ static void lb_vboot_handoff(struct lb_header *header)
 	vbho->size = sizeof(*vbho);
 	vbho->range_start = (intptr_t)addr;
 	vbho->range_size = size;
-}
-#else
-static inline void lb_vboot_handoff(struct lb_header *header) {}
 #endif /* CONFIG_VBOOT_VERIFY_FIRMWARE */
+}
 #endif /* CONFIG_CHROMEOS */
 
+static void lb_board_id(struct lb_header *header)
+{
+#if CONFIG_BOARD_ID_SUPPORT
+	struct lb_board_id  *bid;
+
+	bid = (struct lb_board_id *)lb_new_record(header);
+
+	bid->tag = LB_TAG_BOARD_ID;
+	bid->size = sizeof(*bid);
+	bid->board_id = board_id();
+#endif
+}
+
 static void lb_x86_rom_cache(struct lb_header *header)
 {
 #if CONFIG_ARCH_X86
@@ -574,6 +586,10 @@ unsigned long write_coreboot_table(
 	/* pass along the vboot_handoff address. */
 	lb_vboot_handoff(head);
 #endif
+
+	/* Add board ID if available */
+	lb_board_id(head);
+
 	add_cbmem_pointers(head);
 
 	/* Add board-specific table entries, if any. */