From b03f85f3a27f9524a5a7bfb933a747787cadf488 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Tue, 28 Jan 2025 17:01:33 +0000
Subject: [PATCH] soc/intel/tigerlake: Change the maximum C state to C8
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The EDS says that Tiger Lake "supports C0, C2, C3, C6, C8,
and C10 package states". Update the highest state for non-S0ix
boards accordingly.

Change-Id: I3fe0f5a8f9b52a44d1951037d74df4a244ba602e
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86199
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/tigerlake/acpi.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/soc/intel/tigerlake/acpi.c b/src/soc/intel/tigerlake/acpi.c
index dd9ef731a3..14286f7746 100644
--- a/src/soc/intel/tigerlake/acpi.c
+++ b/src/soc/intel/tigerlake/acpi.c
@@ -102,7 +102,7 @@ static const acpi_cstate_t cstate_map[NUM_C_STATES] = {
 static int cstate_set_non_s0ix[] = {
 	C_STATE_C1,
 	C_STATE_C6_LONG_LAT,
-	C_STATE_C7S_LONG_LAT
+	C_STATE_C8
 };
 
 static int cstate_set_s0ix[] = {