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drivers/amd/opensil/mpio: Factor out common MPIO symbols from vendorcode

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Refactor vendorcode MPIO configuration functions to be invoked from
the openSIL driver.

Change-Id: I8b1f92f08565216dd93203a06015e3eec1e7bb69
Signed-off-by: Nicolas Kochlowski <nickkochlowski@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85632
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Nicolas Kochlowski 2024-12-23 12:22:22 -03:00 • committed by Felix Held
commit afeec465f1
18 changed files with 200 additions and 163 deletions
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4
src/vendorcode/amd/opensil/Kconfig
View file

@ -25,8 +25,8 @@ config AMD_OPENSIL_PATH
config AMD_OPENSIL_MPIO_CHIP_H_FILE
string "Location of specific MPIO chip.h implementation"
default "../../genoa_poc/mpio/chip.h" if SOC_AMD_OPENSIL_GENOA_POC
default "../../stub/mpio/chip.h"
default "$(top)/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.h" if SOC_AMD_OPENSIL_GENOA_POC
default "$(top)/src/vendorcode/amd/opensil/stub/mpio/chip.h"
help
Set to the location of the MPIO chip.h in the selected openSIL
implementation, so that the common MPIO chip.h file can include the

8
src/vendorcode/amd/opensil/chip/mpio/chip.h
View file

@ -1,8 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef OPENSIL_MPIO_CHIP_H
#define OPENSIL_MPIO_CHIP_H
#include CONFIG_AMD_OPENSIL_MPIO_CHIP_H_FILE
#endif /* OPENSIL_MPIO_CHIP_H */

75
src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c
View file

@ -1,37 +1,19 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <RcMgr/DfX/RcManager4-api.h>
#include <NBIO/NbioClass-api.h>
#include <Mpio/MpioClass-api.h>
#include <Mpio/Common/MpioStructs.h>
#include <device/device.h>
#include <device/pci_def.h>
#include <Mpio/Common/MpioStructs.h>
#include <Mpio/MpioClass-api.h>
#include <NBIO/NbioClass-api.h>
#include <RcMgr/DfX/RcManager4-api.h>
#include <vendorcode/amd/opensil/opensil.h>
#include <xSIM-api.h>
#include "chip.h"
#include "../../opensil.h"
struct chip_operations vendorcode_amd_opensil_chip_mpio_ops = {
.name = "AMD GENOA MPIO",
};
static void nbio_config(void)
{
NBIOCLASS_DATA_BLOCK *nbio_data = SilFindStructure(SilId_NbioClass, 0);
NBIOCLASS_INPUT_BLK *input = &nbio_data->NbioInputBlk;
input->CfgHdAudioEnable = false;
input->EsmEnableAllRootPorts = false;
input->EsmTargetSpeed = 16;
input->CfgRxMarginPersistenceMode = 1;
input->CfgDxioFrequencyVetting = false;
input->CfgSkipPspMessage = 1;
input->CfgEarlyTrainTwoPcieLinks = false;
input->EarlyBmcLinkTraining = true;
input->EdpcEnable = 0;
input->PcieAerReportMechanism = 2;
input->SevSnpSupport = false;
}
static void mpio_global_config(MPIOCLASS_INPUT_BLK *mpio_data)
static void mpio_params_config(void)
{
MPIOCLASS_INPUT_BLK *mpio_data = SilFindStructure(SilId_MpioClass, 0);
mpio_data->CfgDxioClockGating = 1;
mpio_data->PcieDxioTimingControlEnable = 0;
mpio_data->PCIELinkReceiverDetectionPolling = 0;
@ -104,7 +86,23 @@ static void mpio_global_config(MPIOCLASS_INPUT_BLK *mpio_data)
/* TODO handle this differently on multisocket */
mpio_data->PcieTopologyData.PlatformData[0].Flags = DESCRIPTOR_TERMINATE_LIST;
mpio_data->PcieTopologyData.PlatformData[0].PciePortList = mpio_data->PcieTopologyData.PortList;
}
static void nbio_params_config(void)
{
NBIOCLASS_DATA_BLOCK *nbio_data = SilFindStructure(SilId_NbioClass, 0);
NBIOCLASS_INPUT_BLK *input = &nbio_data->NbioInputBlk;
input->CfgHdAudioEnable = false;
input->EsmEnableAllRootPorts = false;
input->EsmTargetSpeed = 16;
input->CfgRxMarginPersistenceMode = 1;
input->CfgDxioFrequencyVetting = false;
input->CfgSkipPspMessage = 1;
input->CfgEarlyTrainTwoPcieLinks = false;
input->EarlyBmcLinkTraining = true;
input->EdpcEnable = 0;
input->PcieAerReportMechanism = 2;
input->SevSnpSupport = false;
}
static void setup_bmc_lanes(uint8_t lane, uint8_t socket)
@ -125,12 +123,18 @@ static void setup_bmc_lanes(uint8_t lane, uint8_t socket)
mpio_data->EarlyBmcLinkDie = 0;
}
static void per_device_config(MPIOCLASS_INPUT_BLK *mpio_data, struct device *dev)
void opensil_mpio_per_device_config(struct device *dev)
{
/* Cache *mpio_data from SilFindStructure */
static MPIOCLASS_INPUT_BLK *mpio_data = NULL;
if (mpio_data == NULL) {
mpio_data = SilFindStructure(SilId_MpioClass, 0);
}
static uint32_t slot_num;
const uint32_t domain = dev_get_domain_id(dev);
const uint32_t devfn = dev->path.pci.devfn;
const struct vendorcode_amd_opensil_chip_mpio_config *const config = dev->chip_info;
const struct drivers_amd_opensil_mpio_config *const config = dev->chip_info;
printk(BIOS_DEBUG, "Setting MPIO port for domain 0x%x, PCI %d:%d\n",
domain, PCI_SLOT(devfn), PCI_FUNC(devfn));
@ -191,15 +195,8 @@ static void per_device_config(MPIOCLASS_INPUT_BLK *mpio_data, struct device *dev
mpio_port++;
}
void configure_mpio(void)
void opensil_mpio_global_config(void)
{
MPIOCLASS_INPUT_BLK *mpio_data = SilFindStructure(SilId_MpioClass, 0);
mpio_global_config(mpio_data);
nbio_config();
/* Find all devices with this chip that are directly below the chip */
for (struct device *dev = &dev_root; dev; dev = dev->next)
if (dev->chip_ops == &vendorcode_amd_opensil_chip_mpio_ops &&
dev->chip_info != dev->upstream->dev->chip_info)
per_device_config(mpio_data, dev);
mpio_params_config();
nbio_params_config();
}

2
src/vendorcode/amd/opensil/genoa_poc/mpio/chip.h
View file

@ -54,7 +54,7 @@ enum pcie_aspm {
L0sL1,
};
struct vendorcode_amd_opensil_chip_mpio_config {
struct drivers_amd_opensil_mpio_config {
enum mpio_type type;
uint8_t start_lane;
uint8_t end_lane;

2
src/vendorcode/amd/opensil/genoa_poc/ramstage.c
View file

@ -12,6 +12,7 @@
#include <static.h>
#include <stdio.h>
#include <xSIM-api.h>
#include "opensil_console.h"
#include "../opensil.h"
@ -128,7 +129,6 @@ void setup_opensil(void)
setup_rc_manager_default();
configure_usb();
configure_sata();
configure_mpio();
}
static void opensil_entry(SIL_TIMEPOINT timepoint)

5
src/vendorcode/amd/opensil/opensil.h
View file

@ -12,11 +12,12 @@ void add_opensil_memmap(struct device *dev, unsigned long *idx);
// Fill in FADT from openSIL
void opensil_fill_fadt_io_ports(acpi_fadt_t *fadt);
void configure_mpio(void);
void setup_opensil(void);
void opensil_xSIM_timepoint_1(void);
void opensil_xSIM_timepoint_2(void);
void opensil_xSIM_timepoint_3(void);
void opensil_mpio_global_config(void);
void opensil_mpio_per_device_config(struct device *dev);
#endif

14
src/vendorcode/amd/opensil/stub/mpio/chip.c
View file

@ -1,8 +1,16 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <device/device.h>
#include <vendorcode/amd/opensil/opensil.h>
#include "chip.h"
struct chip_operations vendorcode_amd_opensil_chip_mpio_ops = {
.name = "AMD openSIL stub MPIO",
};
void opensil_mpio_global_config(void)
{
printk(BIOS_NOTICE, "openSIL stub: %s\n", __func__);
}
void opensil_mpio_per_device_config(struct device *dev)
{
printk(BIOS_NOTICE, "openSIL stub: %s\n", __func__);
}

2
src/vendorcode/amd/opensil/stub/mpio/chip.h
View file

@ -60,7 +60,7 @@ enum pcie_slot_power_limit_scale {
SLOT_POWER_LIMIT_DIVISOR_1000 = 3, /* Scale factor 0.001 */
};
struct vendorcode_amd_opensil_chip_mpio_config {
struct drivers_amd_opensil_mpio_config {
enum mpio_engine_type type;
uint8_t start_lane;
uint8_t end_lane;