From afaef0b904057aa848f50f55a7b8ae0b8ebb38d2 Mon Sep 17 00:00:00 2001 From: Appukuttan V K Date: Thu, 21 Aug 2025 12:14:16 +0530 Subject: [PATCH] mainboard/google/ocelot: Update GPIO configuration for SLP_S0_GATE This commit updates the GPIO configuration for the Ocelot baseboard variant. It changes the definition of `GPIO_SLP_S0_GATE` from being not connected (0) to `GPP_C08`. This GPIO will be used as an indicator for the EC. References: - Schematic version: schematic_1433518 BUG=b:440270606 TEST=Perform an S0ix sequence on the system and verify that the power state is properly reported on the EC console. Change-Id: I303322f233824e6980ff6078e62f66eba36203ed Signed-off-by: Appukuttan V K Reviewed-on: https://review.coreboot.org/c/coreboot/+/88875 Reviewed-by: Pranava Y N Reviewed-by: Sowmya Aralguppe Reviewed-by: sridhar siricilla Reviewed-by: Paul Menzel Reviewed-by: Krishna P Bhat D Reviewed-by: Usha P Tested-by: build bot (Jenkins) --- .../ocelot/variants/baseboard/ocelot/include/baseboard/gpio.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/ocelot/variants/baseboard/ocelot/include/baseboard/gpio.h b/src/mainboard/google/ocelot/variants/baseboard/ocelot/include/baseboard/gpio.h index ddc771eed8..cf5924634d 100644 --- a/src/mainboard/google/ocelot/variants/baseboard/ocelot/include/baseboard/gpio.h +++ b/src/mainboard/google/ocelot/variants/baseboard/ocelot/include/baseboard/gpio.h @@ -17,6 +17,6 @@ #define EC_SYNC_IRQ 0 /* Not Connected */ #endif #define GPIO_PCH_WP GPP_D02 -#define GPIO_SLP_S0_GATE 0 /* Not Connected */ +#define GPIO_SLP_S0_GATE GPP_C08 #endif /* __BASEBOARD_GPIO_H__ */