From af2d11f96328dd2fd16be8c4881f7b536736bec4 Mon Sep 17 00:00:00 2001 From: Frank Wu Date: Tue, 25 Feb 2025 16:11:08 +0800 Subject: [PATCH] mb/google/fatcat/var/francka: Adjust NVMe SSD power sequence Move SSD enable/reset pins to romstage to have more time for initialization. BUG=b:398070426 BRANCH=None TEST=Build francka and do EC reset to check the SSD boots to OS successfully Change-Id: I468ba34a54046ef6ed3d5ec4c625a87bb5255640 Signed-off-by: Frank Wu Reviewed-on: https://review.coreboot.org/c/coreboot/+/86593 Reviewed-by: Ian Feng Reviewed-by: Kapil Porwal Reviewed-by: Dtrain Hsu Reviewed-by: Subrata Banik Tested-by: build bot (Jenkins) --- src/mainboard/google/fatcat/variants/francka/gpio.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/mainboard/google/fatcat/variants/francka/gpio.c b/src/mainboard/google/fatcat/variants/francka/gpio.c index 6265b1667d..f2868fc638 100644 --- a/src/mainboard/google/fatcat/variants/francka/gpio.c +++ b/src/mainboard/google/fatcat/variants/francka/gpio.c @@ -416,6 +416,8 @@ static const struct pad_config early_gpio_table[] = { /* Pad configuration in romstage */ static const struct pad_config romstage_gpio_table[] = { + /* GPP_B16: SOC_SSD2_EN */ + PAD_CFG_GPO(GPP_B16, 1, PLTRST), /* GPP_C00: SOC_SMBCLK */ PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1), /* GPP_C01: SOC_SMBDATA */ @@ -424,6 +426,8 @@ static const struct pad_config romstage_gpio_table[] = { PAD_CFG_GPO(GPP_H03, 0, DEEP), /* GPP_H17: FP_RST_1V8_OD# */ PAD_CFG_GPO(GPP_H17, 0, DEEP), + /* GPP_E03: SOC_SSD2_RST# */ + PAD_CFG_GPO(GPP_E03, 1, PLTRST), }; const struct pad_config *variant_gpio_table(size_t *num)