From aee21f53cc9fc1571692e10f74d70264d986d431 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Sat, 24 Jan 2026 09:50:08 +0100 Subject: [PATCH] soc/amd/common/block/cpu/smm: Move microcode load Load microcode from CBFS before setting up MTRRs using x86_setup_mtrrs_with_detect(), since it will remove caching the SPI flash MMIO area and thus slow down CBFS accesses. TEST=Booted on AMD/crater with CBFS_VERIFICATION enabled. The system boots 6msec faster than before. Change-Id: I3fafb98c1348daa549448707db88954316a12ff2 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/90891 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Felix Held --- src/soc/amd/common/block/cpu/smm/smm_relocate.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/soc/amd/common/block/cpu/smm/smm_relocate.c b/src/soc/amd/common/block/cpu/smm/smm_relocate.c index e5b8d9d17a..4ca8911e2a 100644 --- a/src/soc/amd/common/block/cpu/smm/smm_relocate.c +++ b/src/soc/amd/common/block/cpu/smm/smm_relocate.c @@ -17,10 +17,11 @@ /* AP MTRRs will be synced to the BSP in the SIPI vector so set them up before MP init. */ static void pre_mp_init(void) { - x86_setup_mtrrs_with_detect(); - x86_mtrr_check(); if (CONFIG(SOC_AMD_COMMON_BLOCK_UCODE)) amd_load_microcode_from_cbfs(); + + x86_setup_mtrrs_with_detect(); + x86_mtrr_check(); } static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,