From ad05c65d723b893c890ada12b16bc5c77d79ebae Mon Sep 17 00:00:00 2001 From: Jincheng Li Date: Thu, 15 May 2025 14:43:49 +0800 Subject: [PATCH] soc/intel/xeon_sp: Initialize SPI before using it fast_spi_cache_bios_region() refers to the SPI BAR before it is initialized. Therefore, move the initialization before this function to obtain the correct value. If SPI is not initialized before use, an incorrect MTRR item is observed: [DEBUG] 0x00000000fffff005: PHYBASE2: Address = 0x00000000fffff000, WP [DEBUG] 0x000ffffffffff800: PHYMASK2: Length = 0x0000000000001000, Valid TESTED=Build and boot on intel/avenuecity CRB, with below log: [DEBUG] 0x00000000ff000005: PHYBASE2: Address = 0x00000000ff000000, WP [DEBUG] 0x000fffffff000800: PHYMASK2: Length = 0x0000000001000000, Valid Change-Id: I8a755d2d18a567c09c5a66b03d4fdda5ba603133 Signed-off-by: Jincheng Li Reviewed-on: https://review.coreboot.org/c/coreboot/+/88046 Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) Reviewed-by: Shuo Liu --- src/soc/intel/xeon_sp/bootblock.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/xeon_sp/bootblock.c b/src/soc/intel/xeon_sp/bootblock.c index 3e9922f6e9..49548ed9ef 100644 --- a/src/soc/intel/xeon_sp/bootblock.c +++ b/src/soc/intel/xeon_sp/bootblock.c @@ -73,6 +73,7 @@ asmlinkage void bootblock_c_entry(uint64_t base_timestamp) */ assembly_timestamp = base_timestamp; bootblock_timestamp = timestamp_get(); + fast_spi_early_init(SPI_BASE_ADDRESS); fast_spi_cache_bios_region(); bootblock_main_with_basetime(MIN(assembly_timestamp, bootblock_timestamp)); @@ -80,7 +81,6 @@ asmlinkage void bootblock_c_entry(uint64_t base_timestamp) void bootblock_soc_early_init(void) { - fast_spi_early_init(SPI_BASE_ADDRESS); pch_enable_lpc(); /* Set up P2SB BAR. This is needed for PCR to work */