From ab42fceadc7a2d2d802463611cf2e1b1b2f06cf2 Mon Sep 17 00:00:00 2001
From: Alicja Michalska <alicja.michalska@9elements.com>
Date: Tue, 10 Feb 2026 19:20:17 +0100
Subject: [PATCH] MAINTAINERS: Add myself as maintainer for Intel TGL and PTL

I would like to stay on track for everything regarding PantherLake,
given I'm working alongside Intel's engineers to support this SoC
properly.

TigerLake is just a formality, there are only two maintainers currently
and not many systems supported. I own the only TGL-H system in the tree
(erying/tgl) and ELDRID (Google/Volteer baseboard) with TGL-UP3.

Change-Id: I4849aa85787528086e247d9aec8be6138523f5a7
Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91150
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 MAINTAINERS | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 083f91e9e6..2c21b764e9 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -927,12 +927,14 @@ M:	Pranava Y N <pranavayn@google.com>
 M:	Jayvik Desai <jayvik@google.com>
 M:	Avi Uday <aviuday@google.com>
 M:	Dinesh Gehlot <digehlot@google.com>
+M:	Alicja Michalska <alicja.michalska@9elements.com>
 S:	Maintained
 F:	src/soc/intel/pantherlake/
 
 INTEL TIGERLAKE SOC
 M:	Subrata Banik <subratabanik@google.com>
 M:	Nick Vaccaro <nvaccaro@chromium.org>
+M:	Alicja Michalska <alicja.michalska@9elements.com>
 S:	Maintained
 F:	src/soc/intel/tigerlake/