From a9c2d7ff3afa1e2a10be85ccc72b7db0f2aaafe1 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Thu, 1 May 2014 12:46:30 -0700 Subject: [PATCH] broadwell: Unify chip.h and add chip.c Pull together all the used register definitions from the cpu/northbridge/southbridge chip.h files into one structure for the broadwell SOC. Add a chip.c file that contains the main chip_operations structure as well as a shared pci_operations structure that can be used by other ramstage drivers. The chip broadwell_enable function handles different bus types and splits the work out to the right subsystem. BUG=chrome-os-partner:28234 TEST=None Change-Id: I42ceed278b3cd5c46c2384c3f6528246a2193cc8 Signed-off-by: Duncan Laurie Reviewed-on: https://chromium-review.googlesource.com/198917 Reviewed-by: Aaron Durbin --- src/soc/intel/broadwell/chip.c | 82 ++++++++++++++++ src/soc/intel/broadwell/chip.h | 133 ++++++++++++++++++++++---- src/soc/intel/broadwell/systemagent.c | 65 ------------- 3 files changed, 195 insertions(+), 85 deletions(-) create mode 100644 src/soc/intel/broadwell/chip.c diff --git a/src/soc/intel/broadwell/chip.c b/src/soc/intel/broadwell/chip.c new file mode 100644 index 0000000000..94f7893ede --- /dev/null +++ b/src/soc/intel/broadwell/chip.c @@ -0,0 +1,82 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include + +static void pci_domain_set_resources(device_t dev) +{ + assign_resources(dev->link_list); +} + +static struct device_operations pci_domain_ops = { + .read_resources = &pci_domain_read_resources, + .set_resources = &pci_domain_set_resources, + .scan_bus = &pci_domain_scan_bus, + .ops_pci_bus = &pci_ops_mmconf, +}; + +static void cpu_bus_noop(device_t dev) { } + +static struct device_operations cpu_bus_ops = { + .read_resources = &cpu_bus_noop, + .set_resources = &cpu_bus_noop, + .enable_resources = &cpu_bus_noop, + .init = &broadwell_init_cpus, +}; + +static void broadwell_enable(device_t dev) +{ + /* Set the operations if it is a special bus type */ + if (dev->path.type == DEVICE_PATH_DOMAIN) { + dev->ops = &pci_domain_ops; + } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { + dev->ops = &cpu_bus_ops; + } else if (dev->path.type == DEVICE_PATH_PCI) { + /* Handle PCH device enable */ + if (PCI_SLOT(dev->path.pci.devfn) > SA_DEV_SLOT_MINIHD && + (dev->ops == NULL || dev->ops->enable == NULL)) { + broadwell_pch_enable_dev(dev); + } + } +} + +struct chip_operations soc_intel_broadwell_ops = { + CHIP_NAME("Intel Broadwell") + .enable_dev = &broadwell_enable, + .init = &broadwell_init_pre_device, +}; + +static void pci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +{ + if (!vendor || !device) + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + pci_read_config32(dev, PCI_VENDOR_ID)); + else + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + (device << 16) | vendor); +} + +struct pci_operations broadwell_pci_ops = { + .set_subsystem = &pci_set_subsystem +}; diff --git a/src/soc/intel/broadwell/chip.h b/src/soc/intel/broadwell/chip.h index 117bed4e03..a3b716b3bc 100644 --- a/src/soc/intel/broadwell/chip.h +++ b/src/soc/intel/broadwell/chip.h @@ -18,27 +18,120 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* - * Digital Port Hotplug Enable: - * 0x04 = Enabled, 2ms short pulse - * 0x05 = Enabled, 4.5ms short pulse - * 0x06 = Enabled, 6ms short pulse - * 0x07 = Enabled, 100ms short pulse - */ -struct northbridge_intel_haswell_config { - u8 gpu_dp_b_hotplug; /* Digital Port B Hotplug Config */ - u8 gpu_dp_c_hotplug; /* Digital Port C Hotplug Config */ - u8 gpu_dp_d_hotplug; /* Digital Port D Hotplug Config */ +#ifndef _SOC_INTEL_BROADWELL_CHIP_H_ +#define _SOC_INTEL_BROADWELL_CHIP_H_ - u8 gpu_panel_port_select; /* 0=LVDS 1=DP_B 2=DP_C 3=DP_D */ - u8 gpu_panel_power_cycle_delay; /* T4 time sequence */ - u16 gpu_panel_power_up_delay; /* T1+T2 time sequence */ - u16 gpu_panel_power_down_delay; /* T3 time sequence */ - u16 gpu_panel_power_backlight_on_delay; /* T5 time sequence */ - u16 gpu_panel_power_backlight_off_delay; /* Tx time sequence */ +struct soc_intel_broadwell_config { + /* + * Interrupt Routing configuration + * If bit7 is 1, the interrupt is disabled. + */ + uint8_t pirqa_routing; + uint8_t pirqb_routing; + uint8_t pirqc_routing; + uint8_t pirqd_routing; + uint8_t pirqe_routing; + uint8_t pirqf_routing; + uint8_t pirqg_routing; + uint8_t pirqh_routing; - u32 gpu_cpu_backlight; /* CPU Backlight PWM value */ - u32 gpu_pch_backlight; /* PCH Backlight PWM value */ + /* GPE configuration */ + uint32_t gpe0_en_1; + uint32_t gpe0_en_2; + uint32_t gpe0_en_3; + uint32_t gpe0_en_4; + + /* GPIO SMI configuration */ + uint32_t alt_gp_smi_en; + + /* IDE configuration */ + uint8_t sata_port_map; + uint32_t sata_port0_gen3_tx; + uint32_t sata_port1_gen3_tx; + uint32_t sata_port0_gen3_dtle; + uint32_t sata_port1_gen3_dtle; + + /* + * SATA DEVSLP Mux + * 0 = port 0 DEVSLP on DEVSLP0/GPIO33 + * 1 = port 3 DEVSLP on DEVSLP0/GPIO33 + */ + uint8_t sata_devslp_mux; + + /* + * DEVSLP Disable + * 0: DEVSLP is enabled + * 1: DEVSLP is disabled + */ + uint8_t sata_devslp_disable; + + /* Generic IO decode ranges */ + uint32_t gen1_dec; + uint32_t gen2_dec; + uint32_t gen3_dec; + uint32_t gen4_dec; + + /* Enable linear PCIe Root Port function numbers starting at zero */ + uint8_t pcie_port_coalesce; + + /* Force root port ASPM configuration with port bitmap */ + uint8_t pcie_port_force_aspm; + + /* Put SerialIO devices into ACPI mode instead of a PCI device */ + uint8_t sio_acpi_mode; + + /* I2C voltage select: 0=3.3V 1=1.8V */ + uint8_t sio_i2c0_voltage; + uint8_t sio_i2c1_voltage; + + /* + * Clock Disable Map: + * [21:16] = CLKOUT_PCIE# 5-0 + * [24] = CLKOUT_ITPXDP + */ + uint32_t icc_clock_disable; + + /* + * Digital Port Hotplug Enable: + * 0x04 = Enabled, 2ms short pulse + * 0x05 = Enabled, 4.5ms short pulse + * 0x06 = Enabled, 6ms short pulse + * 0x07 = Enabled, 100ms short pulse + */ + u8 gpu_dp_b_hotplug; + u8 gpu_dp_c_hotplug; + u8 gpu_dp_d_hotplug; + + /* Panel power sequence timings */ + u8 gpu_panel_port_select; + u8 gpu_panel_power_cycle_delay; + u16 gpu_panel_power_up_delay; + u16 gpu_panel_power_down_delay; + u16 gpu_panel_power_backlight_on_delay; + u16 gpu_panel_power_backlight_off_delay; + + /* Panel backlight settings */ + u32 gpu_cpu_backlight; + u32 gpu_pch_backlight; + + /* + * Graphics CD Clock Frequency + * 0 = 337.5MHz + * 1 = 450MHz + * 2 = 540MHz + * 3 = 675MHz + */ + int cdclk; + + /* Enable S0iX support */ + int s0ix_enable; + + /* TCC activation offset */ + int tcc_offset; }; -extern struct chip_operations northbridge_intel_haswell_ops; +typedef struct soc_intel_broadwell_config config_t; + +extern struct chip_operations soc_ops; + +#endif diff --git a/src/soc/intel/broadwell/systemagent.c b/src/soc/intel/broadwell/systemagent.c index 52f3bb617d..7e8133c64d 100644 --- a/src/soc/intel/broadwell/systemagent.c +++ b/src/soc/intel/broadwell/systemagent.c @@ -69,28 +69,6 @@ static int get_pcie_bar(device_t dev, unsigned int index, u32 *base, u32 *len) return 0; } -static void pci_domain_set_resources(device_t dev) -{ - assign_resources(dev->link_list); -} - - /* TODO We could determine how many PCIe busses we need in - * the bar. For now that number is hardcoded to a max of 64. - * See e7525/northbridge.c for an example. - */ -static struct device_operations pci_domain_ops = { - .read_resources = pci_domain_read_resources, - .set_resources = pci_domain_set_resources, - .enable_resources = NULL, - .init = NULL, - .scan_bus = pci_domain_scan_bus, -#if CONFIG_MMCONF_SUPPORT_DEFAULT - .ops_pci_bus = &pci_ops_mmconf, -#else - .ops_pci_bus = &pci_cf8_conf1, -#endif -}; - static int get_bar(device_t dev, unsigned int index, u32 *base, u32 *len) { u32 bar; @@ -497,46 +475,3 @@ static struct device_operations mc_ops = { .ops_pci = &intel_pci_ops, }; -static const struct pci_driver mc_driver_hsw_mobile __pci_driver = { - .ops = &mc_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_HSW_MOBILE, -}; - -static const struct pci_driver mc_driver_hsw_ult __pci_driver = { - .ops = &mc_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_HSW_ULT, -}; - -static void cpu_bus_init(device_t dev) -{ - bsp_init_and_start_aps(dev->link_list); -} - -static void cpu_bus_noop(device_t dev) -{ -} - -static struct device_operations cpu_bus_ops = { - .read_resources = cpu_bus_noop, - .set_resources = cpu_bus_noop, - .enable_resources = cpu_bus_noop, - .init = cpu_bus_init, - .scan_bus = 0, -}; - -static void enable_dev(device_t dev) -{ - /* Set the operations if it is a special bus type */ - if (dev->path.type == DEVICE_PATH_DOMAIN) { - dev->ops = &pci_domain_ops; - } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { - dev->ops = &cpu_bus_ops; - } -} - -struct chip_operations northbridge_intel_haswell_ops = { - CHIP_NAME("Intel i7 (Haswell) integrated Northbridge") - .enable_dev = enable_dev, -};