diff --git a/src/soc/intel/xeon_sp/ibl/soc_pch.c b/src/soc/intel/xeon_sp/ibl/soc_pch.c index 7487441242..ee66c0d0cb 100644 --- a/src/soc/intel/xeon_sp/ibl/soc_pch.c +++ b/src/soc/intel/xeon_sp/ibl/soc_pch.c @@ -1,40 +1,28 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include -#include #include #include -#include +#include #include -#define PCR_PSF3_TO_SHDW_PMC_REG_BASE 0x600 -#define PCR_PSFX_TO_SHDW_BAR4 0x10 -#define PCR_PSFX_TO_SHDW_PCIEN_IOEN 0x01 -#define PCR_PSFX_T0_SHDW_PCIEN 0x1C - static void soc_config_acpibase(void) { - uint32_t pmc_reg_value; - uint32_t pmc_base_reg = PCR_PSF3_TO_SHDW_PMC_REG_BASE; + /* Disable IO command in PMC Device first before changing Base Address */ + uint16_t reg16 = pci_read_config16(PCH_DEV_PMC, PCI_COMMAND); + pci_write_config16(PCH_DEV_PMC, PCI_COMMAND, + reg16 & ~(PCI_COMMAND_IO | PCI_COMMAND_MASTER)); - pmc_reg_value = pcr_read32(PID_PSF3, pmc_base_reg + PCR_PSFX_TO_SHDW_BAR4); + /* Program ACPI Base */ + pci_write_config32(PCH_DEV_PMC, ABASE, ACPI_BASE_ADDRESS); - if (pmc_reg_value != 0xffffffff) { - /* Disable Io Space before changing the address */ - pcr_rmw32(PID_PSF3, pmc_base_reg + PCR_PSFX_T0_SHDW_PCIEN, - ~PCR_PSFX_TO_SHDW_PCIEN_IOEN, 0); - /* Program ABASE in PSF3 PMC space BAR4*/ - pcr_write32(PID_PSF3, pmc_base_reg + PCR_PSFX_TO_SHDW_BAR4, - ACPI_BASE_ADDRESS); - /* Enable IO Space */ - pcr_rmw32(PID_PSF3, pmc_base_reg + PCR_PSFX_T0_SHDW_PCIEN, - ~0, PCR_PSFX_TO_SHDW_PCIEN_IOEN); - } /* Enable Bus Master and IO Space */ pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, (PCI_COMMAND_IO | PCI_COMMAND_MASTER)); - uint16_t data = pcr_read16(PID_PSF3, pmc_base_reg + PCR_PSFX_TO_SHDW_BAR4); + uint32_t data = pci_read_config32(PCH_DEV_PMC, ABASE); + assert(ACPI_BASE_ADDRESS == (data & ~PCI_BASE_ADDRESS_IO_ATTR_MASK)); printk(BIOS_INFO, "%s : pmbase = %x\n", __func__, (int)data); }