From a8139c0b87053dbe9868da01c8e64e64e62786e3 Mon Sep 17 00:00:00 2001 From: Maximilian Brune Date: Mon, 24 Feb 2025 17:21:35 +0100 Subject: [PATCH] treewide: Rename PM4LE -> PML4E MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The x86 (AMD and Intel) spec defines it as Page-Map Level-4 Entry. It is annoying when searching for the wrong abbreviation in the spec so fix it everywhere it occurs. source: Intel 64 spec April 2022 and AMD64 spec April 2024. Signed-off-by: Maximilian Brune Change-Id: I730235beea69b3720f080bbade083c2eeed26587 Reviewed-on: https://review.coreboot.org/c/coreboot/+/86587 Reviewed-by: Jérémy Compostella Reviewed-by: Patrick Rudolph Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Benjamin Doron Reviewed-by: Andy Ebrahiem --- payloads/libpayload/arch/x86/head_64.S | 4 ++-- payloads/libpayload/arch/x86/pt.S | 8 ++++---- src/cpu/intel/car/core2/cache_as_ram.S | 2 +- src/cpu/intel/car/non-evict/cache_as_ram.S | 2 +- src/cpu/intel/car/p4-netburst/cache_as_ram.S | 2 +- src/cpu/x86/64bit/mode_switch2.S | 2 +- src/cpu/x86/64bit/pt.S | 4 ++-- src/cpu/x86/64bit/pt1G.S | 4 ++-- src/cpu/x86/smm/smm_module_loader.c | 10 +++++----- src/soc/amd/common/block/cpu/noncar/pre_c.S | 2 +- src/soc/intel/common/block/cpu/car/cache_as_ram.S | 2 +- src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S | 2 +- 12 files changed, 22 insertions(+), 22 deletions(-) diff --git a/payloads/libpayload/arch/x86/head_64.S b/payloads/libpayload/arch/x86/head_64.S index 65242749fa..1fd0d01e7a 100644 --- a/payloads/libpayload/arch/x86/head_64.S +++ b/payloads/libpayload/arch/x86/head_64.S @@ -70,7 +70,7 @@ _entry: movl %eax, cb_header_ptr call init_page_table - movl $pm4le, %eax + movl $pml4e, %eax /* load identity mapped page tables */ movl %eax, %cr3 @@ -107,7 +107,7 @@ _init64: movq %rdi, cb_header_ptr call init_page_table - movq $pm4le, %rax + movq $pml4e, %rax /* load identity mapped page tables */ movq %rax, %cr3 diff --git a/payloads/libpayload/arch/x86/pt.S b/payloads/libpayload/arch/x86/pt.S index 0e6e7bffef..080d044b84 100644 --- a/payloads/libpayload/arch/x86/pt.S +++ b/payloads/libpayload/arch/x86/pt.S @@ -41,10 +41,10 @@ #define _D (1ULL << 6) #define _PS (1ULL << 7) -.section .bss.pm4le -.global pm4le +.section .bss.pml4e +.global pml4e .align 4096 -pm4le: +pml4e: .skip 8 .section .bss.main_page_table @@ -144,6 +144,6 @@ no_overflow_1gb: leave: or $(_PRES + _RW + _US + _A), %eax - mov %eax, pm4le + mov %eax, pml4e ret diff --git a/src/cpu/intel/car/core2/cache_as_ram.S b/src/cpu/intel/car/core2/cache_as_ram.S index 227ddf4c22..de945a9396 100644 --- a/src/cpu/intel/car/core2/cache_as_ram.S +++ b/src/cpu/intel/car/core2/cache_as_ram.S @@ -163,7 +163,7 @@ addrsize_set_high: subl $4, %esp #if ENV_X86_64 - setup_longmode $PM4LE + setup_longmode $PML4E movd %mm2, %rdi shlq $32, %rdi diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S index 9485cd44fb..7186422595 100644 --- a/src/cpu/intel/car/non-evict/cache_as_ram.S +++ b/src/cpu/intel/car/non-evict/cache_as_ram.S @@ -214,7 +214,7 @@ end_microcode_update: andl $0xfffffff0, %esp #if ENV_X86_64 - setup_longmode $PM4LE + setup_longmode $PML4E movd %mm2, %rdi shlq $32, %rdi diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S index 1cb422dbfc..1843954539 100644 --- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S +++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S @@ -363,7 +363,7 @@ fill_cache: subl $4, %esp #if ENV_X86_64 - setup_longmode $PM4LE + setup_longmode $PML4E movd %mm2, %rdi shlq $32, %rdi /* BIST */ diff --git a/src/cpu/x86/64bit/mode_switch2.S b/src/cpu/x86/64bit/mode_switch2.S index 18c6425d7f..3be56c4c5a 100644 --- a/src/cpu/x86/64bit/mode_switch2.S +++ b/src/cpu/x86/64bit/mode_switch2.S @@ -21,7 +21,7 @@ long_mode_call_3arg: mov %esp, %ebp /* Enter long mode, preserves ebx */ - setup_longmode $PM4LE + setup_longmode $PML4E /* Align stack */ movabs $0xfffffffffffffff0, %rax diff --git a/src/cpu/x86/64bit/pt.S b/src/cpu/x86/64bit/pt.S index 4b2f3c8163..1297296a37 100644 --- a/src/cpu/x86/64bit/pt.S +++ b/src/cpu/x86/64bit/pt.S @@ -17,9 +17,9 @@ #define _GEN_DIR(a) (_PRES + _RW + _US + _A + (a)) #define _GEN_PAGE(a) (_PRES + _RW + _US + _PS + _A + _D + (a)) -.global PM4LE +.global PML4E .align 4096 -PM4LE: +PML4E: .quad _GEN_DIR(PDPT) .align 4096 diff --git a/src/cpu/x86/64bit/pt1G.S b/src/cpu/x86/64bit/pt1G.S index 3502964d15..42cdfb17d0 100644 --- a/src/cpu/x86/64bit/pt1G.S +++ b/src/cpu/x86/64bit/pt1G.S @@ -17,9 +17,9 @@ #define _GEN_DIR(a) (_PRES + _RW + _US + _A + (a)) #define _GEN_PAGE(a) (_PRES + _RW + _US + _PS + _A + _D + (a)) -.global PM4LE +.global PML4E .align 4096 -PM4LE: +PML4E: .quad _GEN_DIR(PDPT) .align 4096 diff --git a/src/cpu/x86/smm/smm_module_loader.c b/src/cpu/x86/smm/smm_module_loader.c index c6d0753c6b..ba92e1ff2f 100644 --- a/src/cpu/x86/smm/smm_module_loader.c +++ b/src/cpu/x86/smm/smm_module_loader.c @@ -420,27 +420,27 @@ static int append_and_check_region(const struct region smram, #define _GEN_PAGE(a) (_PRES + _RW + _US + _PS + _A + _D + (a)) #define PAGE_SIZE 8 -/* Return the PM4LE */ +/* Return the PML4E */ static uintptr_t install_page_table(const uintptr_t handler_base) { const bool one_g_pages = !!(cpuid_edx(0x80000001) & (1 << 26)); /* 4 1G pages or 4 PDPE entries with 512 * 2M pages */ const size_t pages_needed = one_g_pages ? 4 : 2048 + 4; const uintptr_t pages_base = ALIGN_DOWN(handler_base - pages_needed * PAGE_SIZE, 4096); - const uintptr_t pm4le = ALIGN_DOWN(pages_base - 8, 4096); + const uintptr_t pml4e = ALIGN_DOWN(pages_base - 8, 4096); if (one_g_pages) { for (size_t i = 0; i < 4; i++) write64p(pages_base + i * PAGE_SIZE, _GEN_PAGE(1ull * GiB * i)); - write64p(pm4le, _GEN_DIR(pages_base)); + write64p(pml4e, _GEN_DIR(pages_base)); } else { for (size_t i = 0; i < 2048; i++) write64p(pages_base + i * PAGE_SIZE, _GEN_PAGE(2ull * MiB * i)); - write64p(pm4le, _GEN_DIR(pages_base + 2048 * PAGE_SIZE)); + write64p(pml4e, _GEN_DIR(pages_base + 2048 * PAGE_SIZE)); for (size_t i = 0; i < 4; i++) write64p(pages_base + (2048 + i) * PAGE_SIZE, _GEN_DIR(pages_base + 4096 * i)); } - return pm4le; + return pml4e; } /* diff --git a/src/soc/amd/common/block/cpu/noncar/pre_c.S b/src/soc/amd/common/block/cpu/noncar/pre_c.S index 0e0be524f2..b75458815e 100644 --- a/src/soc/amd/common/block/cpu/noncar/pre_c.S +++ b/src/soc/amd/common/block/cpu/noncar/pre_c.S @@ -28,7 +28,7 @@ bootblock_pre_c_entry: post_code(POSTCODE_BOOTBLOCK_PRE_C_ENTRY) #if ENV_X86_64 - setup_longmode $PM4LE + setup_longmode $PML4E #endif /* Clear .bss section */ diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index 2c4beebf46..b84a06e0ba 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -280,7 +280,7 @@ car_init_done: andl $0xfffffff0, %esp #if ENV_X86_64 - setup_longmode $PM4LE + setup_longmode $PML4E movd %mm2, %rdi shlq $32, %rdi diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S index 4e057f046d..ed735dbce3 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S @@ -83,7 +83,7 @@ CAR_init_done: movl %ecx, temp_memory_start #if ENV_X86_64 - setup_longmode $PM4LE + setup_longmode $PML4E movl %ebp, %edi shlq $32, %rdi movd %mm1, %rsi