From a7db71744771decc04cf1966efba70bf4897cfa3 Mon Sep 17 00:00:00 2001 From: David Hendricks Date: Wed, 29 Jan 2014 18:22:17 -0800 Subject: [PATCH] tegra124/nyan*: Obtain DRAM size dynamically This eliminates CONFIG_DRAM_SIZE_MB and uses helper functions to determine DRAM size dynamically. It impacts MMU setup and BCT selection in romstage, along with framebuffer setup in ramstage. BUG=none BRANCH=none TEST=built and booted on Nyan Signed-off-by: David Hendricks Change-Id: I41e6b24b853b856026fc26f3b1ee8edf2333ad3c Reviewed-on: https://chromium-review.googlesource.com/184431 Reviewed-by: Julius Werner Tested-by: David Hendricks Commit-Queue: David Hendricks --- src/mainboard/google/nyan/Kconfig | 4 ---- src/mainboard/google/nyan/romstage.c | 19 +++++++++++-------- src/mainboard/google/nyan_big/Kconfig | 4 ---- src/mainboard/google/nyan_big/romstage.c | 19 +++++++++++-------- src/soc/nvidia/tegra/dc.h | 3 +++ src/soc/nvidia/tegra124/Makefile.inc | 1 + src/soc/nvidia/tegra124/cbmem.c | 3 ++- src/soc/nvidia/tegra124/display.c | 8 +++++++- .../nvidia/tegra124/include/soc/addressmap.h | 5 +---- src/soc/nvidia/tegra124/soc.c | 6 ++++-- 10 files changed, 40 insertions(+), 32 deletions(-) diff --git a/src/mainboard/google/nyan/Kconfig b/src/mainboard/google/nyan/Kconfig index 811bca564e..1fa4f26a9a 100644 --- a/src/mainboard/google/nyan/Kconfig +++ b/src/mainboard/google/nyan/Kconfig @@ -40,10 +40,6 @@ config MAINBOARD_PART_NUMBER string default "Nyan" -config DRAM_SIZE_MB - int - default 2048 - config DRAM_DMA_START hex default 0x90000000 diff --git a/src/mainboard/google/nyan/romstage.c b/src/mainboard/google/nyan/romstage.c index 8d8e6a95ce..16804ac95a 100644 --- a/src/mainboard/google/nyan/romstage.c +++ b/src/mainboard/google/nyan/romstage.c @@ -26,14 +26,10 @@ #include #include #include "soc/nvidia/tegra124/chip.h" +#include "soc/nvidia/tegra124/sdram.h" #include #include -// Convenient shorthand (in MB) -#define DRAM_START (CONFIG_SYS_SDRAM_BASE >> 20) -#define DRAM_SIZE CONFIG_DRAM_SIZE_MB -#define DRAM_END (DRAM_START + DRAM_SIZE) /* plus one... */ - enum { L2CTLR_ECC_PARITY = 0x1 << 21, L2CTLR_TAG_RAM_LATENCY_MASK = 0x7 << 6, @@ -74,6 +70,7 @@ static void configure_l2actlr(void) static void __attribute__((noinline)) romstage(void) { + int dram_size_mb; #if CONFIG_COLLECT_TIMESTAMPS uint64_t romstage_start_time = timestamp_get(); #endif @@ -84,12 +81,18 @@ static void __attribute__((noinline)) romstage(void) console_init(); exception_init(); + /* used for MMU and CBMEM setup */ + dram_size_mb = sdram_size_mb(); + + u32 dram_start = (CONFIG_SYS_SDRAM_BASE >> 20); + u32 dram_end = dram_start + dram_size_mb; /* plus one... */ + mmu_init(); - mmu_config_range(0, DRAM_START, DCACHE_OFF); - mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK); + mmu_config_range(0, dram_start, DCACHE_OFF); + mmu_config_range(dram_start, dram_size_mb, DCACHE_WRITEBACK); mmu_config_range(CONFIG_DRAM_DMA_START >> 20, CONFIG_DRAM_DMA_SIZE >> 20, DCACHE_OFF); - mmu_config_range(DRAM_END, 4096 - DRAM_END, DCACHE_OFF); + mmu_config_range(dram_end, 4096 - dram_end, DCACHE_OFF); mmu_disable_range(0, 1); dcache_mmu_enable(); diff --git a/src/mainboard/google/nyan_big/Kconfig b/src/mainboard/google/nyan_big/Kconfig index 2a735a60d7..1a07b19520 100644 --- a/src/mainboard/google/nyan_big/Kconfig +++ b/src/mainboard/google/nyan_big/Kconfig @@ -40,10 +40,6 @@ config MAINBOARD_PART_NUMBER string default "Nyan Big" -config DRAM_SIZE_MB - int - default 2048 - config DRAM_DMA_START hex default 0x90000000 diff --git a/src/mainboard/google/nyan_big/romstage.c b/src/mainboard/google/nyan_big/romstage.c index c013d11ea9..01dddd9e20 100644 --- a/src/mainboard/google/nyan_big/romstage.c +++ b/src/mainboard/google/nyan_big/romstage.c @@ -26,14 +26,10 @@ #include #include #include "soc/nvidia/tegra124/chip.h" +#include "soc/nvidia/tegra124/sdram.h" #include #include -// Convenient shorthand (in MB) -#define DRAM_START (CONFIG_SYS_SDRAM_BASE >> 20) -#define DRAM_SIZE CONFIG_DRAM_SIZE_MB -#define DRAM_END (DRAM_START + DRAM_SIZE) /* plus one... */ - enum { L2CTLR_ECC_PARITY = 0x1 << 21, L2CTLR_TAG_RAM_LATENCY_MASK = 0x7 << 6, @@ -74,6 +70,7 @@ static void configure_l2actlr(void) static void __attribute__((noinline)) romstage(void) { + int dram_size_mb; #if CONFIG_COLLECT_TIMESTAMPS uint64_t romstage_start_time = timestamp_get(); #endif @@ -84,12 +81,18 @@ static void __attribute__((noinline)) romstage(void) console_init(); exception_init(); + /* used for MMU and CBMEM setup */ + dram_size_mb = sdram_size_mb(); + + u32 dram_start = (CONFIG_SYS_SDRAM_BASE >> 20); + u32 dram_end = dram_start + dram_size_mb; /* plus one... */ + mmu_init(); - mmu_config_range(0, DRAM_START, DCACHE_OFF); - mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK); + mmu_config_range(0, dram_start, DCACHE_OFF); + mmu_config_range(dram_start, dram_size_mb, DCACHE_WRITEBACK); mmu_config_range(CONFIG_DRAM_DMA_START >> 20, CONFIG_DRAM_DMA_SIZE >> 20, DCACHE_OFF); - mmu_config_range(DRAM_END, 4096 - DRAM_END, DCACHE_OFF); + mmu_config_range(dram_end, 4096 - dram_end, DCACHE_OFF); mmu_disable_range(0, 1); dcache_mmu_enable(); diff --git a/src/soc/nvidia/tegra/dc.h b/src/soc/nvidia/tegra/dc.h index 7a38adf0a0..48ffbda356 100644 --- a/src/soc/nvidia/tegra/dc.h +++ b/src/soc/nvidia/tegra/dc.h @@ -569,4 +569,7 @@ struct disp_ctl_win { void display_startup(device_t dev); void dp_bringup(u32 winb_addr); + +unsigned int fb_base_mb(void); + #endif /* __SOC_NVIDIA_TEGRA_DC_H */ diff --git a/src/soc/nvidia/tegra124/Makefile.inc b/src/soc/nvidia/tegra124/Makefile.inc index 687d37df66..93c06d3016 100644 --- a/src/soc/nvidia/tegra124/Makefile.inc +++ b/src/soc/nvidia/tegra124/Makefile.inc @@ -45,6 +45,7 @@ ramstage-y += dma.c ramstage-y += i2c.c ramstage-y += maincpu.S ramstage-y += monotonic_timer.c +ramstage-y += sdram.c ramstage-y += soc.c ramstage-y += sor.c ramstage-y += spi.c diff --git a/src/soc/nvidia/tegra124/cbmem.c b/src/soc/nvidia/tegra124/cbmem.c index d80b3a03cd..3226c978f7 100644 --- a/src/soc/nvidia/tegra124/cbmem.c +++ b/src/soc/nvidia/tegra124/cbmem.c @@ -19,9 +19,10 @@ #include #include +#include void *cbmem_top(void) { return (void *)(CONFIG_SYS_SDRAM_BASE + - ((CONFIG_DRAM_SIZE_MB - FB_SIZE_MB)<< 20UL)); + ((sdram_size_mb() - FB_SIZE_MB)<< 20UL)); } diff --git a/src/soc/nvidia/tegra124/display.c b/src/soc/nvidia/tegra124/display.c index ba357fd245..00dfbb694d 100644 --- a/src/soc/nvidia/tegra124/display.c +++ b/src/soc/nvidia/tegra124/display.c @@ -33,6 +33,7 @@ #include #include #include +#include #include "chip.h" #include @@ -225,6 +226,11 @@ static void update_window(struct display_controller *dc, WRITEL(val, &dc->cmd.state_ctrl); } +uint32_t fb_base_mb(void) +{ + return CONFIG_SYS_SDRAM_BASE/MiB + (sdram_size_mb() - FB_SIZE_MB); +} + /* this is really aimed at the lcd panel. That said, there are two display * devices on this part and we may someday want to extend it for other boards. */ @@ -279,7 +285,7 @@ void display_startup(device_t dev) } if (! framebuffer_base_mb) - framebuffer_base_mb = FB_BASE_MB; + framebuffer_base_mb = fb_base_mb(); mmu_config_range(framebuffer_base_mb, framebuffer_size_mb, config->cache_policy); diff --git a/src/soc/nvidia/tegra124/include/soc/addressmap.h b/src/soc/nvidia/tegra124/include/soc/addressmap.h index 5e55ee57e0..d67ba111cb 100644 --- a/src/soc/nvidia/tegra124/include/soc/addressmap.h +++ b/src/soc/nvidia/tegra124/include/soc/addressmap.h @@ -80,9 +80,6 @@ enum { TEGRA_I2C_BASE_COUNT = 6, }; -enum { - FB_SIZE_MB = (32), - FB_BASE_MB = (CONFIG_SYS_SDRAM_BASE/MiB + (CONFIG_DRAM_SIZE_MB - FB_SIZE_MB)), -}; +#define FB_SIZE_MB (32) #endif /* __SOC_NVIDIA_TEGRA124_INCLUDE_SOC_ADDRESS_MAP_H__ */ diff --git a/src/soc/nvidia/tegra124/soc.c b/src/soc/nvidia/tegra124/soc.c index e996c110aa..779418c234 100644 --- a/src/soc/nvidia/tegra124/soc.c +++ b/src/soc/nvidia/tegra124/soc.c @@ -22,6 +22,7 @@ #include #include #include +#include #include /* this sucks, but for now, fb size/location are hardcoded. @@ -30,10 +31,11 @@ */ static void soc_enable(device_t dev) { + u32 lcdbase = fb_base_mb(); unsigned long fb_size = FB_SIZE_MB; - u32 lcdbase = FB_BASE_MB; + ram_resource(dev, 0, CONFIG_SYS_SDRAM_BASE/KiB, - (CONFIG_DRAM_SIZE_MB - fb_size)*KiB); + (sdram_size_mb() - fb_size)*KiB); mmio_resource(dev, 1, lcdbase*KiB, fb_size*KiB); }