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falco: Remove RTD2312 chip and setup from devicetree

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This disables the spread spectrum clock and avoids errata.

BUG=chrome-os-partner:22077
BRANCH=falco
TEST=emerge-falco chromeos-coreboot-falco

Change-Id: I04eb767f1587bb64a215a92b66cd05e099d29964
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/66673
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Duncan Laurie 2013-08-22 10:19:25 -07:00 • committed by ChromeBot
commit a7bf0d818c
1 changed files with 1 additions and 28 deletions
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29
src/mainboard/google/falco/devicetree.cb
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@ -114,34 +114,7 @@ chip northbridge/intel/haswell
end
end # LPC bridge
device pci 1f.2 on end # SATA Controller
device pci 1f.3 on # SMBus
chip drivers/i2c/rtd2132
# Panel Power Timings (1 ms units)
# Note: the panel Tx timings are very
# different from the LVDS bridge
# Tx timing settings. Below is a mapping
# for RTD2132 -> Panel timings.
# T1 = T2
# T2 = T8 + T10 + T12
# T3 = T14
# T4 = T15
# T5 = T9 + T11 + T13
# T6 = T3
# T7 = T4
register "t1" = "20"
register "t2" = "16"
register "t3" = "1"
register "t4" = "1"
register "t5" = "16"
register "t6" = "20"
register "t7" = "500"
# LVDS Swap settings are normal.
register "lvds_swap" = "0"
# Enable Spread Sprectrum at 0.5%
register "sscg_percent" = "0x05"
device i2c 35 on end
end
end
device pci 1f.3 on end # SMBus
device pci 1f.6 on end # Thermal
end
end