From a66d2d41f5e79b5e9715d85bcbf251c3a4029c63 Mon Sep 17 00:00:00 2001 From: Nicholas Chin Date: Sat, 21 Jun 2025 09:05:43 -0600 Subject: [PATCH] mb/lenovo/m900/devicetree.cb: Use OC6 enum MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Commit 0e5d1d29bde9 ("soc/intel/skylake: Expand USB OC pins enum to OC7") added the missing OC6 and OC7 enums for PCH-H, so use those instead of a bare integer to map USB2 ports 10 and 11 to overcurrent pin 6. TEST=Timeless build did not change Change-Id: I3680fae39e96783e4434b36a8dfd751888541cbb Signed-off-by: Nicholas Chin Reviewed-on: https://review.coreboot.org/c/coreboot/+/88160 Tested-by: build bot (Jenkins) Reviewed-by: Michał Kopeć Reviewed-by: Matt DeVillier --- src/mainboard/lenovo/m900/devicetree.cb | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/lenovo/m900/devicetree.cb b/src/mainboard/lenovo/m900/devicetree.cb index 8b550a74d3..b5c02cca0f 100644 --- a/src/mainboard/lenovo/m900/devicetree.cb +++ b/src/mainboard/lenovo/m900/devicetree.cb @@ -54,8 +54,8 @@ chip soc/intel/skylake [7] = USB2_PORT_MID(OC3), /* Rear port 4 */ [8] = USB2_PORT_MID(OC5), /* FUSB_1 Header */ [9] = USB2_PORT_MID(OC5), /* FUSB_1 Header */ - [10] = USB2_PORT_MID(6), /* FUSB_2 Header */ - [11] = USB2_PORT_MID(6), /* FUSB_2 Header */ + [10] = USB2_PORT_MID(OC6), /* FUSB_2 Header */ + [11] = USB2_PORT_MID(OC6), /* FUSB_2 Header */ [12] = USB2_PORT_MID(OC1), /* Rear port 7 */ [13] = USB2_PORT_MID(OC1), /* Rear port 8 */ }"