UPSTREAM: soc/intel/skylake: Move update microcode from cbfs to mp_ops callbacks

FIT is already loading microcode before CPU Reset. So, we need
not update the microcode again in RO FW in bootblock.

But we need to update in RW FW if there is any new ucode version.
So, added the update microcode function in get_microcode_info callback
before MP Init to make sure BSP is using the microcode from cbfs.

BUG=none
BRANCH=none
TEST=Build and Boot poppy

Change-Id: I7665b2f1fc10f625f8535aef1f11a77154dfe2a4
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 682355ab16
Original-Change-Id: I5606563726c00974f00285acfa435cadc90a085e
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Reviewed-on: https://review.coreboot.org/20051
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/531703
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>

src/soc/intel/skylake/bootblock/cpu.c

@@ -16,7 +16,7 @@
 
 #include <arch/io.h>
 #include <console/console.h>
-#include <cpu/intel/microcode/microcode.c>
+#include <cpu/x86/msr.h>
 #include <delay.h>
 #include <intelblocks/fast_spi.h>
 #include <reset.h>
@@ -89,7 +89,6 @@ void bootblock_cpu_init(void)
 	fast_spi_cache_bios_region();
 	/* Set flex ratio and reset if needed */
 	set_flex_ratio_to_tdp_nominal();
-	intel_update_microcode_from_cbfs();
 }
 
 void set_max_freq(void)

src/soc/intel/skylake/cpu.c

@@ -480,6 +480,7 @@ static void get_microcode_info(const void **microcode, int *parallel)
 	microcode_patch = intel_microcode_find();
 	*microcode = microcode_patch;
 	*parallel = 1;
+	intel_microcode_load_unlocked(microcode_patch);
 }
 
 static int adjust_apic_id(int index, int apic_id)