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UPSTREAM: soc/intel/common: Enable MTRR display during bootblock & postcar

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Update Makefile.inc to allow MTRR display during bootblock and postcar.

TEST=Build and run on Galileo Gen2

BUG=None
BRANCH=None

Change-Id: I994302ccf8a7c2dd092f762bdab92bcc12d33769
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15990
Tested-by: build bot (Jenkins)
Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/366295
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
This commit is contained in:
Lee Leahy 2016-07-30 07:17:13 -07:00 • committed by chrome-bot
commit 9ffa27b6c8
1 changed files with 4 additions and 0 deletions
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4
src/soc/intel/common/Makefile.inc
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@ -1,5 +1,7 @@
ifeq ($(CONFIG_SOC_INTEL_COMMON),y)
bootblock-y += util.c
verstage-$(CONFIG_SOC_INTEL_COMMON_LPSS_I2C) += lpss_i2c.c
verstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c
@ -12,6 +14,8 @@ romstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c
romstage-y += util.c
romstage-$(CONFIG_MMA) += mma.c
postcar-y += util.c
ramstage-y += hda_verb.c
ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c
ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += nvm.c