From 9ffa27b6c8b9ddc7537eca28f1f067214f5c8dfb Mon Sep 17 00:00:00 2001 From: Lee Leahy Date: Sat, 30 Jul 2016 07:17:13 -0700 Subject: [PATCH] UPSTREAM: soc/intel/common: Enable MTRR display during bootblock & postcar Update Makefile.inc to allow MTRR display during bootblock and postcar. TEST=Build and run on Galileo Gen2 BUG=None BRANCH=None Change-Id: I994302ccf8a7c2dd092f762bdab92bcc12d33769 Signed-off-by: Lee Leahy Reviewed-on: https://review.coreboot.org/15990 Tested-by: build bot (Jenkins) Reviewed-by: Kysti Mlkki Reviewed-on: https://chromium-review.googlesource.com/366295 Commit-Ready: Furquan Shaikh Tested-by: Furquan Shaikh Reviewed-by: Furquan Shaikh --- src/soc/intel/common/Makefile.inc | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc index 429c61c2e1..13ba21bcbe 100644 --- a/src/soc/intel/common/Makefile.inc +++ b/src/soc/intel/common/Makefile.inc @@ -1,5 +1,7 @@ ifeq ($(CONFIG_SOC_INTEL_COMMON),y) +bootblock-y += util.c + verstage-$(CONFIG_SOC_INTEL_COMMON_LPSS_I2C) += lpss_i2c.c verstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c @@ -12,6 +14,8 @@ romstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c romstage-y += util.c romstage-$(CONFIG_MMA) += mma.c +postcar-y += util.c + ramstage-y += hda_verb.c ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += nvm.c