From 9e7c787f6db38a2b0ca0631615d7683c0bb2cba6 Mon Sep 17 00:00:00 2001 From: Kirubakaran E Date: Wed, 18 Mar 2026 00:02:50 -0700 Subject: [PATCH] soc/qualcomm/x1p42100: Add 806 MHz CPU clock definition Add the required definition for the 806 MHz CPU clock (L_VAL_806MHz). Update pll_init_and_set by removing the static qualifier so it can be invoked from the mainboard code. Test: Built image.serial.bin and verified successful boot on X1P42100. Change-Id: I8871f6cd64cb386c1042ce42feec4c623e9804e9 Signed-off-by: Kirubakaran E Reviewed-on: https://review.coreboot.org/c/coreboot/+/91722 Reviewed-by: Subrata Banik Reviewed-by: Kapil Porwal Tested-by: build bot (Jenkins) --- src/soc/qualcomm/x1p42100/clock.c | 2 +- src/soc/qualcomm/x1p42100/include/soc/clock.h | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/src/soc/qualcomm/x1p42100/clock.c b/src/soc/qualcomm/x1p42100/clock.c index eba4987217..76e964831f 100644 --- a/src/soc/qualcomm/x1p42100/clock.c +++ b/src/soc/qualcomm/x1p42100/clock.c @@ -612,7 +612,7 @@ enum cb_err usb_clock_configure_mux(enum clk_pipe_usb clk_type, u32 src_type) return CB_SUCCESS; } -static enum cb_err pll_init_and_set(struct x1p42100_ncc0_clock *ncc0, u32 l_val) +enum cb_err pll_init_and_set(struct x1p42100_ncc0_clock *ncc0, u32 l_val) { int ret; struct alpha_pll_reg_val_config ncc0_pll_cfg = {0}; diff --git a/src/soc/qualcomm/x1p42100/include/soc/clock.h b/src/soc/qualcomm/x1p42100/include/soc/clock.h index c126baac62..474852940b 100644 --- a/src/soc/qualcomm/x1p42100/include/soc/clock.h +++ b/src/soc/qualcomm/x1p42100/include/soc/clock.h @@ -20,6 +20,7 @@ /* CPU PLL*/ #define L_VAL_1363P2MHz 0x47 +#define L_VAL_806MHz 0x2A /* DISP PLL */ #define L_VAL_1725MHz 0x59 @@ -892,6 +893,7 @@ enum cb_err mdss_clock_enable(enum clk_mdss clk_type); enum cb_err disp_pll_init_and_set(struct x1p42100_disp_pll_clock *disp_pll, u32 l_val, u32 alpha_val); enum cb_err lpass_init(void); +enum cb_err pll_init_and_set(struct x1p42100_ncc0_clock *ncc0, u32 l_val); void clock_configure_dfsr_table_x1p42100(int qup, struct clock_freq_config *clk_cfg, uint32_t num_perfs);