From 9e5c7eb3f8751377afafcfc31380fde91947ca0d Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Fri, 25 Jul 2025 10:14:08 +0200 Subject: [PATCH] soc/amd/glinda: Add XGBE devices Some specific Glinda SoCs support dual 10G PCI ethernet devices. Add defines and chipset entries for XGBE0 and XGBE1. Signed-off-by: Maximilian Brune Change-Id: I7e3bb1819165a7c2f4284b76450f831bb99b1ad3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/90416 Reviewed-by: Felix Held Tested-by: build bot (Jenkins) --- src/soc/amd/glinda/chipset.cb | 2 ++ src/soc/amd/glinda/include/soc/pci_devs.h | 8 ++++++++ 2 files changed, 10 insertions(+) diff --git a/src/soc/amd/glinda/chipset.cb b/src/soc/amd/glinda/chipset.cb index 853e05250f..e72cfb971b 100644 --- a/src/soc/amd/glinda/chipset.cb +++ b/src/soc/amd/glinda/chipset.cb @@ -60,6 +60,8 @@ chip soc/amd/glinda ops amd_internal_pcie_gpp_ops device pci 0.0 on end # dummy, do not disable device pci 0.1 alias npu off end # Neural Processing Unit (NPU) + device pci 0.2 alias xgbe_0 off end # 10 GbE Controller Port 0 (XGBE0) + device pci 0.3 alias xgbe_1 off end # 10 GbE Controller Port 1 (XGBE1) end device pci 08.3 alias gpp_bridge_c on # Internal GPP Bridge 2 to Bus C diff --git a/src/soc/amd/glinda/include/soc/pci_devs.h b/src/soc/amd/glinda/include/soc/pci_devs.h index e85a6e3372..222addb00c 100644 --- a/src/soc/amd/glinda/include/soc/pci_devs.h +++ b/src/soc/amd/glinda/include/soc/pci_devs.h @@ -81,6 +81,14 @@ #define PCIE_GPP_B_DEVFN PCI_DEVFN(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_B_FUNC) #define SOC_PCIE_GPP_B_DEV _SOC_DEV(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_B_FUNC) +#define XGBE0_DEV 0x0 +#define XGBE0_FUNC 2 +#define XGBE0_DEVFN PCI_DEVFN(XGBE0_DEV, XGBE0_FUNC) + +#define XGBE1_DEV 0x0 +#define XGBE1_FUNC 3 +#define XGBE1_DEVFN PCI_DEVFN(XGBE1_DEV, XGBE1_FUNC) + #define PCIE_ABC_C_FUNC 3 #define PCIE_ABC_C_DEVFN PCI_DEVFN(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_C_FUNC) #define SOC_PCIE_GPP_C_DEV _SOC_DEV(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_C_FUNC)