diff --git a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h
index 68137490b9..9538e3bf06 100644
--- a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h
+++ b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h
@@ -3,7 +3,7 @@
 #ifndef SOC_INTEL_COMMON_BLOCK_PCIE_RP_H
 #define SOC_INTEL_COMMON_BLOCK_PCIE_RP_H
 
-#include <stdint.h>
+#include <types.h>
 
 /*
  * In schematic PCIe root port numbers are 1-based, but FSP use 0-based indexes for
@@ -85,6 +85,24 @@ struct pcie_rp_config {
 	enum PCIE_SPEED_control pcie_rp_pcie_speed;
 };
 
+struct pcie_modphy_config {
+	/* TX Output Downscale Amplitude Adjustment */
+	bool tx_gen1_downscale_amp_override;
+	uint8_t tx_gen1_downscale_amp;
+	/* TX Output Downscale Amplitude Adjustment */
+	bool tx_gen2_downscale_amp_override;
+	uint8_t tx_gen2_downscale_amp;
+	/* TX Output Downscale Amplitude Adjustment */
+	bool tx_gen3_downscale_amp_override;
+	uint8_t tx_gen3_downscale_amp;
+	/* TX Output -3.5dB Mode De-Emphasis Adjustment Setting */
+	uint8_t tx_gen1_de_emph;
+	/* TX Output -3.5dB Mode De-Emphasis Adjustment Setting */
+	uint8_t tx_gen2_de_emph_3p5;
+	/* TX Output -6.0dB Mode De-Emphasis Adjustment Setting */
+	uint8_t tx_gen2_de_emph_6p0;
+};
+
 /*
  * The PCIe Root Ports usually come in groups of up to 8 PCI-device
  * functions.
diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h
index 380549451e..3fdf82db97 100644
--- a/src/soc/intel/jasperlake/chip.h
+++ b/src/soc/intel/jasperlake/chip.h
@@ -15,7 +15,6 @@
 #include <soc/gpe.h>
 #include <soc/pch.h>
 #include <soc/pci_devs.h>
-#include <soc/pcie_modphy.h>
 #include <soc/pmc.h>
 #include <soc/serialio.h>
 #include <soc/usb.h>
diff --git a/src/soc/intel/jasperlake/include/soc/pcie_modphy.h b/src/soc/intel/jasperlake/include/soc/pcie_modphy.h
deleted file mode 100644
index 60f145195f..0000000000
--- a/src/soc/intel/jasperlake/include/soc/pcie_modphy.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef _SOC_JASPERLAKE_PCIE_MODPHY_H_
-#define _SOC_JASPERLAKE_PCIE_MODPHY_H_
-
-struct pcie_modphy_config {
-	/* TX Output Downscale Amplitude Adjustment */
-	bool tx_gen1_downscale_amp_override;
-	uint8_t tx_gen1_downscale_amp;
-	/* TX Output Downscale Amplitude Adjustment */
-	bool tx_gen2_downscale_amp_override;
-	uint8_t tx_gen2_downscale_amp;
-	/* TX Output Downscale Amplitude Adjustment */
-	bool tx_gen3_downscale_amp_override;
-	uint8_t tx_gen3_downscale_amp;
-	/* TX Output -3.5dB Mode De-Emphasis Adjustment Setting */
-	uint8_t tx_gen1_de_emph;
-	/* TX Output -3.5dB Mode De-Emphasis Adjustment Setting */
-	uint8_t tx_gen2_de_emph_3p5;
-	/* TX Output -6.0dB Mode De-Emphasis Adjustment Setting */
-	uint8_t tx_gen2_de_emph_6p0;
-};
-
-#endif