soc/qualcomm/common: Add API to enable Lucidole PLL for X1P42100

Add API to enable Lucidole PLL.

TEST=Create an image.serial.bin and ensure it boots on X1P42100.

Change-Id: Idfefebcbe57498446e32c75d5c1532d321b8fb74
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90392
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/qualcomm/common/clock.c

@@ -302,6 +302,26 @@ enum cb_err zondaole_pll_enable(struct alpha_pll_reg_val_config *cfg)
 	return CB_SUCCESS;
 }
 
+enum cb_err lucidole_pll_enable(struct alpha_pll_reg_val_config *cfg)
+{
+	/*
+	 * H/W requires a 1us delay between disabling the bypass and
+	 * de-asserting the reset.
+	 */
+	udelay(1);
+	setbits32(cfg->reg_opmode, PLL_RUN_MODE);
+	setbits32(cfg->reg_mode, BIT(PLL_RESET_SHFT));
+
+	if (!wait_us(100, read32(cfg->reg_mode) & PLL_LOCK_DET_BMSK)) {
+		printk(BIOS_ERR, "CPU PLL did not lock!\n");
+		return CB_ERR;
+	}
+
+	setbits32(cfg->reg_mode, BIT(PLL_OUTCTRL_SHFT));
+
+	return CB_SUCCESS;
+}
+
 /* Bring subsystem out of RESET */
 void clock_reset_subsystem(u32 *misc, u32 shft)
 {

src/soc/qualcomm/common/include/soc/clock_common.h

@@ -182,6 +182,8 @@ enum cb_err agera_pll_enable(struct alpha_pll_reg_val_config *cfg);
 
 enum cb_err zonda_pll_enable(struct alpha_pll_reg_val_config *cfg);
 
+enum cb_err lucidole_pll_enable(struct alpha_pll_reg_val_config *cfg);
+
 /*
  * zondaole_pll_enable(): Enable Zondaole PLL at the given configuration (cfg).
  *