added bcm-e100 specific code
This commit is contained in:
Li-Ta Lo
parent
8e6bf09eb3
commit
99836e7a05
6 changed files with 426 additions and 0 deletions
17
src/mainboard/bcm/e100/Config
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17
src/mainboard/bcm/e100/Config
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arch i386
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mainboardinit cpu/i386/entry16.inc
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mainboardinit cpu/i386/entry32.inc
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ldscript cpu/i386/entry16.lds
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ldscript cpu/i386/entry32.lds
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mainboardinit pc80/serial.inc
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mainboardinit arch/i386/lib/console.inc
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northsouthbridge sis/550
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option FINAL_MAINBOARD_FIXUP
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option HAVE_PIRQ_TABLE=1
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object mainboard.o
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object irq_tables.o
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keyboard pc80
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cpu p5
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277
src/mainboard/bcm/e100/ipl.S
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277
src/mainboard/bcm/e100/ipl.S
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@ -0,0 +1,277 @@
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/*
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* ipl.S: Initial Program Loader (IPL) for SiS 550 SoC and M-System DoC Millennium
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*
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*
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* Copyright 2000 Silicon Integrated Systems Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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*
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* Reference:
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* 1. SiS 550 Chipset Registers Version 0.1, Mar. 8, 2001
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* 2. System Management Bus Specification Rev 1.1
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* 3. PC SDRAM Serial Presence Detect (SPD) Specification Rev 1.2B
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* 4. Booting From the DiskOnChip Millennium, M-Systems Application Note Ap-DOC-044
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* APR-2000, 93-SR-001-44-7L REV. 1.0
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*
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* $Id$
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*/
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#include "ipl.h"
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.code16
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#ifdef STD_FLASH
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.org 0xfc00
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#endif
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#undef SIZE_ALL
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#define REALLY_COMPACT
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sis630spd_start:
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cli # Disables the maskable
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# hardware interrupts.
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movw %cs, %ax # makes data segment ==
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movw %ax, %ds # code segment
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movw $lpc_init_table, %si
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lpc_init_start: # inits LPC bridge for accessing
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lodsw (%si), %ax # SMBus and DoC
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testw %ax, %ax
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jz lpc_init_complete
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CALL_SP(write_lpc_register)
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jmp lpc_init_start
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lpc_init_complete:
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movw $0x5501, %ax # MDOE# enable, this bit
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CALL_SP(write_pci_register) # should be set before sizing.
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/* -----------------------------------------------------------------------------------------*/
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gpio_trap_start:
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/* memory sizing by GPIO hardware trap */
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movw $0x5066, %dx
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inb %dx, %al # Read GPIO from ACPI Register 0x66
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testb $0x80, %al # Test if GPIO7 is set
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jz eb_200
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eb_100:
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movw $0x6006, %ax # GPIO7 == 1 ==> EB-100
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CALL_SP(write_pci_register) # 2x12x9 (64MB)
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movw $0x63a1, %ax # enable DIMM 0, SMA 8MB
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CALL_SP(write_pci_register) # write register 0x63
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jmp gpio_trap_end
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eb_200:
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movw $0x6002, %ax # GPIO7 == 0 ==> EB-200
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CALL_SP(write_pci_register) # 2x12x8 (32MB)
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movw $0x6391, %ax # enable DIMM 0, SMA 4MB
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CALL_SP(write_pci_register) # write register 0x63
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gpio_trap_end:
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/* -----------------------------------------------------------------------------------------*/
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movw $pci_init_table, %si
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init_sdram:
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lodsw (%si), %ax
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testw %ax, %ax
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jz init_complete
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CALL_SP(write_pci_register)
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jmp init_sdram
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init_complete:
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/* -----------------------------------------------------------------------------------------*/
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sis630ipl_start:
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/* O.K. we have DRAM now, so set up STACK for CALL/RET */
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movw $DOC_STACK_SEG, %ax
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movw %ax, %ss
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movw $SPL_RAM_SEG, %ax
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movw %ax, %es
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xorw %sp, %sp # clear %sp
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#ifdef STD_FLASH
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#include "rom/std_flash.inc"
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#else /* !STD_FLASH */
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#if (USE_DOC_MIL == 1) || (USE_DOC_2000_TSOP == 1)
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# include "rom/doc_mil.inc"
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#else (USE_DOC_MIL_PLUS == 1)
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# include "rom/doc_mil_plus.inc"
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#endif
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#endif /* STD_FLASH */
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sis630ipl_end:
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jmp spl_vector # jump to SPL vector
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/* -----------------------------------------------------------------------------------------*/
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write_lpc_register:
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/* Input: AH - register number. AL - register value. */
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movl $LPC_BRIDGE_BASE_ADDR, %edx
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jmp write_common
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write_pci_register:
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/* Input: AH - register number. AL - register value. */
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movl $NORTH_BRIDGE_BASE_ADDR, %edx
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write_common:
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movw %ax, %cx # Save %ax to %cx.
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movzbl %ch, %eax # add register address to
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addl %edx, %eax # PCI base address
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movw $PCI_COMMAND_PORT, %dx
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outl %eax, %dx
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movw $PCI_DATA_PORT, %dx
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andb $0x03, %al
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addb %al, %dl
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movw %cx, %ax # Restore %ax
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outb %al, %dx
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RET_SP # End of write_[lpc|pci]_reg
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/* -----------------------------------------------------------------------------------------*/
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read_spd:
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/* Input: AH = 05h, AL = byte number of SPD to be read.
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Output: BL = The value of specified SPD byte. */
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movb $0x05, %ah # set SMB Command == byte address
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CALL_BP(sis_set_smbus)
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movw $0x0312, %ax # Start, R/W byte Data
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CALL_BP(sis_set_smbus)
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wait_for_smbus_read:
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movb $0x80, %dl # Read SMBus status
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inb %dx, %al
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testb $0x02, %al # if device errors
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jnz read_spd_fail # then skip read SPD
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testb $0x08, %al # if not complete
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jz wait_for_smbus_read # then wait SPD data complete
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read_spd_fail:
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movb $0x08, %ah
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sis_get_smbus:
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/* Input: AH - register index.
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Output: BL - register value. */
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addb %ah, %dl # read SMBus byte 0
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inb %dx, %al
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movb %al, %bl # return result in BL
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movw $0x00ff, %ax
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CALL_BP(sis_set_smbus) # clear ACPI 80h status
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RET_SP # End of read_spd
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sis_set_smbus:
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/* Input: AH - register index. AL - register value. */
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movw $SMB_BASE_ADDR, %dx
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addb %ah, %dl
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outb %al, %dx
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RET_BP # End of sis_set_smbus
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/* -----------------------------------------------------------------------------------------*/
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sdram_type_bank_1:
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# Column Number 8 9 10 11 Row Number
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.byte 0b0000, 0b0100, 0b1000, 0xff # 11
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.byte 0xff, 0xff, 0xff, 0xff # 12
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.byte 0b0001, 0b0101, 0b1001, 0b1101 # 13
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sdram_type_bank_2:
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# Column Number 8 9 10 11 Row Number
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.byte 0b1100, 0xff, 0xff, 0xff # 11
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.byte 0b0010, 0b0110, 0b1010, 0b1110 # 12
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.byte 0b0011, 0b0111, 0b1011, 0b1111 # 13
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/* -----------------------------------------------------------------------------------------*/
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lpc_init_table:
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# High Byte -> Register Low Byte -> Value
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.word 0x408a # ACPI Enable, Decode E,F segment
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.word 0x4540 # Flash Write Enable. (for DoC command)
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.word 0x78fc
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.word 0x79fc
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.word 0x7afe
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.word 0x7bfe
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.word 0x7550 # Store ACPI Base Address.
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# (for use of SMBus)
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.word 0x0000 /* Null, End of table */
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pci_init_table:
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# High Byte -> Register Low Byte -> Value
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.word 0x8c44 # SDRCLK/SDWCLK
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.word 0x8d86 # SDWCLK
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.word 0x5780 # Precharge
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.word 0x5200 # Refresh Cycle Disable
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.word 0x5780 # Precharge
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.word 0x5740 # Mode Register Set
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.word 0x5720 # Refresh
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.word 0x5720 # Refresh
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.word 0x5720 # Refresh
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.word 0x5201 # Refresh Cycle Enable
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.word 0x0000 /* Null, End of table */
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/* -----------------------------------------------------------------------------------------*/
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#ifdef STD_FLASH
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.org 0xfff0
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reset_vector:
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.byte 0xea # jmp to f000:fc00, where IPL
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.word 0xfc00, 0xf000 # starts in Standard Flash
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#else /* !STD_FLASH i.e. DoC Mil */
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#if (USE_DOC_MIL == 1)
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.org 0x1f0
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#elif (USE_DOC_2000_TSOP == 1) || (USE_DOC_MIL_PLUS == 1)
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.org 0x3f0
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#endif
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reset_vector:
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.byte 0xea # jmp to fe00:0000, where IPL
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.word 0x0000, DOC_WIN_SEG # starts in DoC
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#endif /* STD_FLASH */
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spl_vector:
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.byte 0xea # jmp to 8000:0000, where SPL
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.word 0x0000, SPL_RAM_SEG # (LinuxBIOS) starts in RAM
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/* -----------------------------------------------------------------------------------------*/
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#ifdef STD_FLASH
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.org 0xffff
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#else /* !STD_FLASH i.e. DoC Mil */
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#if (USE_DOC_MIL == 1)
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.org 0x1ff
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#elif (USE_DOC_2000_TSOP == 1) || (USE_DOC_MIL_PLUS == 1)
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.org 0x3ff
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#endif
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#endif
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end:
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hlt
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42
src/mainboard/bcm/e100/ipl.h
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42
src/mainboard/bcm/e100/ipl.h
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@ -0,0 +1,42 @@
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#define PCI_COMMAND_PORT 0xcf8
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#define PCI_DATA_PORT 0xcfc
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#define NORTH_BRIDGE_BASE_ADDR 0x80000000
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#define LPC_BRIDGE_BASE_ADDR 0x80000800
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#define SMB_BASE_ADDR 0x5080
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#define DOC_WIN_SEG 0xfe00
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#define DOC_STACK_SEG 0x0400
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#define SPL_RAM_SEG 0x8000
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#if (USE_DOC_2000_TSOP == 1)
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#define DOC_SPL_START_PAGE 4 /* 0-3 for IPL (each of 1KB size) */
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#else /* defined (USE_DOC_MIL) */
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#define DOC_SPL_START_PAGE 2 /* 0,1 for IPL (each of 512B size) */
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#endif
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#define DOC_SPL_SIZE_IN_PAGE 128 - DOC_SPL_START_PAGE /* 1 page = 512 bytes, total 63kB */
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#define RET_LABEL(label) \
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jmp label##_done
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#define CALL_LABEL(label) \
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jmp label ;\
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label##_done:
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#define CALL_SP(func) \
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lea 0f, %sp ; \
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jmp func ; \
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0:
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#define RET_SP \
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jmp *%sp
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#define CALL_BP(func) \
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lea 0f, %bp ; \
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jmp func ; \
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0:
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#define RET_BP \
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jmp *%bp
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31
src/mainboard/bcm/e100/irq_tables.c
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31
src/mainboard/bcm/e100/irq_tables.c
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#include <arch/pirq_routing.h>
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#define CHECKSUM 0x1F
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const struct irq_routing_table intel_irq_routing_table = {
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PIRQ_SIGNATURE, /* u32 signature */
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PIRQ_VERSION, /* u16 version */
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32+16*6, /* there can be total 6 devices on the bus */
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0x00, /* Bus 0 */
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0x08, /* Device 1, Function 0 */
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0x0C20, /* reserve IRQ 11, 10, 5, for PCI */
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0x1039, /* Silicon Integrated System */
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0x0008, /* SiS 85C503/5513 ISA Bridge */
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0x00, /* u8 miniport_data - "crap" */
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
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CHECKSUM, /* u8 checksum - mod 256 checksum must give zero */
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{
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/* bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
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{0x00, 0x48, {{0x42, 0xdef8}, {0x43, 0xdef8}, {0x44, 0xdef8}, {0x41, 0xdef8}},
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0x01, 0x00},
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{0x00, 0x58, {{0x43, 0xdef8}, {0x44, 0xdef8}, {0x41, 0xdef8}, {0x42, 0xdef8}},
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0x02, 0x00},
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{0x00, 0x68, {{0x41, 0xdef8}, {0x42, 0xdef8}, {0x43, 0xdef8}, {0x44, 0xdef8}},
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0x03, 0x00},
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{0x00, 0x01, {{0x61, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}},
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0x00, 0x00},
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{0x00, 0x10, {{0x41, 0xdef8}, {0x42, 0xdef8}, {0x43, 0xdef8}, {0x44, 0xdef8}},
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0x00, 0x00},
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{0x00, 0x0a, {{0x41, 0xdef8}, {0x42, 0xdef8}, {0x43, 0xdef8}, {0x44, 0xdef8}},
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0x00, 0x00},
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}
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};
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16
src/mainboard/bcm/e100/mainboard.c
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16
src/mainboard/bcm/e100/mainboard.c
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@ -0,0 +1,16 @@
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#include <printk.h>
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void
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mainboard_fixup(void)
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{
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}
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void
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final_mainboard_fixup(void)
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{
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void final_southbridge_fixup(void);
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printk_info("SiS 550 (and similar)...");
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final_southbridge_fixup();
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}
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43
util/config/bcm-e100.config
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43
util/config/bcm-e100.config
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# Sample config file for SiS 550 SoC with DoC Millennium (as root)
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# This will make a target directory of ./winfast
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target bcm-e100
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# SiS 550 SoC demo mainboard
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mainboard bcm/e100
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# Use 256KB Standard Flash as Normal BIOS
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option USE_GENERIC_ROM=1
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option STD_FLASH
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option ZKERNEL_START=0xfffc0000
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# payload size = 192KB
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option PAYLOAD_SIZE=196608
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# Rom image size = 63KB
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option ROM_IMAGE_SIZE=64512
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# We reuse docipl from DoC
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docipl mainboard/bcm/e100/ipl.S
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# Use the internal VGA frame buffer device
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option HAVE_FRAMEBUFFER
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# use ELF Loader to load Etherboot
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option USE_ELF_BOOT=1
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# Use etherboot as our payload
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payload /home/ollie/work/etherboot/src/bin32/sis900.ebi
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# Add our own special make rules to handle 256KB flash with docipl
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makerule romimage: linuxbios.rom payload.block docipl ;
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addaction romimage cat payload.block linuxbios.rom docipl.bin > romimage
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makerule docipl: ipl.o ;
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addaction docipl objcopy -O binary -R .note -R .comment -S ipl.o docipl
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addaction docipl dd if=docipl skip=126 of=docipl.bin
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addaction clean rm -f docipl.bin
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makerule linuxbios.rom: linuxbios.strip ;
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addaction linuxbios.rom dd if=linuxbios.strip of=linuxbios.rom bs=$(ROM_IMAGE_SIZE) conv=sync
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# Kernel command line parameters
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commandline root=/dev/hda1 console=tty0 video=sisfb:1024x768-32@85,font:VGA8x16
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