From 99836e7a05effe5d7ea2a0539f9c221f5798f83b Mon Sep 17 00:00:00 2001 From: Li-Ta Lo Date: Fri, 31 May 2002 08:46:09 +0000 Subject: [PATCH] added bcm-e100 specific code --- src/mainboard/bcm/e100/Config | 17 ++ src/mainboard/bcm/e100/ipl.S | 277 ++++++++++++++++++++++++++++ src/mainboard/bcm/e100/ipl.h | 42 +++++ src/mainboard/bcm/e100/irq_tables.c | 31 ++++ src/mainboard/bcm/e100/mainboard.c | 16 ++ util/config/bcm-e100.config | 43 +++++ 6 files changed, 426 insertions(+) create mode 100644 src/mainboard/bcm/e100/Config create mode 100644 src/mainboard/bcm/e100/ipl.S create mode 100644 src/mainboard/bcm/e100/ipl.h create mode 100644 src/mainboard/bcm/e100/irq_tables.c create mode 100644 src/mainboard/bcm/e100/mainboard.c create mode 100644 util/config/bcm-e100.config diff --git a/src/mainboard/bcm/e100/Config b/src/mainboard/bcm/e100/Config new file mode 100644 index 0000000000..61da7e2df6 --- /dev/null +++ b/src/mainboard/bcm/e100/Config @@ -0,0 +1,17 @@ +arch i386 +mainboardinit cpu/i386/entry16.inc +mainboardinit cpu/i386/entry32.inc +ldscript cpu/i386/entry16.lds +ldscript cpu/i386/entry32.lds + +mainboardinit pc80/serial.inc +mainboardinit arch/i386/lib/console.inc + +northsouthbridge sis/550 + +option FINAL_MAINBOARD_FIXUP +option HAVE_PIRQ_TABLE=1 +object mainboard.o +object irq_tables.o +keyboard pc80 +cpu p5 diff --git a/src/mainboard/bcm/e100/ipl.S b/src/mainboard/bcm/e100/ipl.S new file mode 100644 index 0000000000..d0be90e77b --- /dev/null +++ b/src/mainboard/bcm/e100/ipl.S @@ -0,0 +1,277 @@ +/* + * ipl.S: Initial Program Loader (IPL) for SiS 550 SoC and M-System DoC Millennium + * + * + * Copyright 2000 Silicon Integrated Systems Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + * + * Reference: + * 1. SiS 550 Chipset Registers Version 0.1, Mar. 8, 2001 + * 2. System Management Bus Specification Rev 1.1 + * 3. PC SDRAM Serial Presence Detect (SPD) Specification Rev 1.2B + * 4. Booting From the DiskOnChip Millennium, M-Systems Application Note Ap-DOC-044 + * APR-2000, 93-SR-001-44-7L REV. 1.0 + * + * $Id$ + */ + +#include "ipl.h" + +.code16 + +#ifdef STD_FLASH +.org 0xfc00 +#endif + +#undef SIZE_ALL +#define REALLY_COMPACT + +sis630spd_start: + cli # Disables the maskable + # hardware interrupts. + + movw %cs, %ax # makes data segment == + movw %ax, %ds # code segment + + movw $lpc_init_table, %si +lpc_init_start: # inits LPC bridge for accessing + lodsw (%si), %ax # SMBus and DoC + testw %ax, %ax + jz lpc_init_complete + + CALL_SP(write_lpc_register) + jmp lpc_init_start + +lpc_init_complete: + + movw $0x5501, %ax # MDOE# enable, this bit + CALL_SP(write_pci_register) # should be set before sizing. + +/* -----------------------------------------------------------------------------------------*/ + +gpio_trap_start: + /* memory sizing by GPIO hardware trap */ + movw $0x5066, %dx + inb %dx, %al # Read GPIO from ACPI Register 0x66 + + testb $0x80, %al # Test if GPIO7 is set + jz eb_200 + +eb_100: + movw $0x6006, %ax # GPIO7 == 1 ==> EB-100 + CALL_SP(write_pci_register) # 2x12x9 (64MB) + + movw $0x63a1, %ax # enable DIMM 0, SMA 8MB + CALL_SP(write_pci_register) # write register 0x63 + + jmp gpio_trap_end + +eb_200: + movw $0x6002, %ax # GPIO7 == 0 ==> EB-200 + CALL_SP(write_pci_register) # 2x12x8 (32MB) + movw $0x6391, %ax # enable DIMM 0, SMA 4MB + CALL_SP(write_pci_register) # write register 0x63 + +gpio_trap_end: + +/* -----------------------------------------------------------------------------------------*/ + + movw $pci_init_table, %si +init_sdram: + lodsw (%si), %ax + testw %ax, %ax + jz init_complete + + CALL_SP(write_pci_register) + jmp init_sdram + +init_complete: + +/* -----------------------------------------------------------------------------------------*/ + +sis630ipl_start: + /* O.K. we have DRAM now, so set up STACK for CALL/RET */ + movw $DOC_STACK_SEG, %ax + movw %ax, %ss + movw $SPL_RAM_SEG, %ax + movw %ax, %es + xorw %sp, %sp # clear %sp + +#ifdef STD_FLASH +#include "rom/std_flash.inc" +#else /* !STD_FLASH */ +#if (USE_DOC_MIL == 1) || (USE_DOC_2000_TSOP == 1) +# include "rom/doc_mil.inc" +#else (USE_DOC_MIL_PLUS == 1) +# include "rom/doc_mil_plus.inc" +#endif +#endif /* STD_FLASH */ + +sis630ipl_end: + jmp spl_vector # jump to SPL vector + +/* -----------------------------------------------------------------------------------------*/ + +write_lpc_register: + /* Input: AH - register number. AL - register value. */ + movl $LPC_BRIDGE_BASE_ADDR, %edx + jmp write_common + +write_pci_register: + /* Input: AH - register number. AL - register value. */ + movl $NORTH_BRIDGE_BASE_ADDR, %edx + +write_common: + movw %ax, %cx # Save %ax to %cx. + + movzbl %ch, %eax # add register address to + addl %edx, %eax # PCI base address + + movw $PCI_COMMAND_PORT, %dx + outl %eax, %dx + + movw $PCI_DATA_PORT, %dx + andb $0x03, %al + addb %al, %dl + movw %cx, %ax # Restore %ax + outb %al, %dx + RET_SP # End of write_[lpc|pci]_reg + +/* -----------------------------------------------------------------------------------------*/ + +read_spd: + /* Input: AH = 05h, AL = byte number of SPD to be read. + Output: BL = The value of specified SPD byte. */ + movb $0x05, %ah # set SMB Command == byte address + CALL_BP(sis_set_smbus) + + movw $0x0312, %ax # Start, R/W byte Data + CALL_BP(sis_set_smbus) + +wait_for_smbus_read: + movb $0x80, %dl # Read SMBus status + inb %dx, %al + + testb $0x02, %al # if device errors + jnz read_spd_fail # then skip read SPD + + testb $0x08, %al # if not complete + jz wait_for_smbus_read # then wait SPD data complete + +read_spd_fail: + movb $0x08, %ah + +sis_get_smbus: + /* Input: AH - register index. + Output: BL - register value. */ + addb %ah, %dl # read SMBus byte 0 + inb %dx, %al + movb %al, %bl # return result in BL + + movw $0x00ff, %ax + CALL_BP(sis_set_smbus) # clear ACPI 80h status + + RET_SP # End of read_spd + +sis_set_smbus: + /* Input: AH - register index. AL - register value. */ + movw $SMB_BASE_ADDR, %dx + addb %ah, %dl + outb %al, %dx + RET_BP # End of sis_set_smbus + +/* -----------------------------------------------------------------------------------------*/ + +sdram_type_bank_1: +# Column Number 8 9 10 11 Row Number + .byte 0b0000, 0b0100, 0b1000, 0xff # 11 + .byte 0xff, 0xff, 0xff, 0xff # 12 + .byte 0b0001, 0b0101, 0b1001, 0b1101 # 13 + +sdram_type_bank_2: +# Column Number 8 9 10 11 Row Number + .byte 0b1100, 0xff, 0xff, 0xff # 11 + .byte 0b0010, 0b0110, 0b1010, 0b1110 # 12 + .byte 0b0011, 0b0111, 0b1011, 0b1111 # 13 + +/* -----------------------------------------------------------------------------------------*/ + +lpc_init_table: +# High Byte -> Register Low Byte -> Value + .word 0x408a # ACPI Enable, Decode E,F segment + .word 0x4540 # Flash Write Enable. (for DoC command) + + .word 0x78fc + .word 0x79fc + .word 0x7afe + .word 0x7bfe + + .word 0x7550 # Store ACPI Base Address. + # (for use of SMBus) + .word 0x0000 /* Null, End of table */ + +pci_init_table: +# High Byte -> Register Low Byte -> Value + .word 0x8c44 # SDRCLK/SDWCLK + .word 0x8d86 # SDWCLK + + .word 0x5780 # Precharge + .word 0x5200 # Refresh Cycle Disable + .word 0x5780 # Precharge + .word 0x5740 # Mode Register Set + .word 0x5720 # Refresh + .word 0x5720 # Refresh + .word 0x5720 # Refresh + .word 0x5201 # Refresh Cycle Enable + .word 0x0000 /* Null, End of table */ + +/* -----------------------------------------------------------------------------------------*/ + +#ifdef STD_FLASH + .org 0xfff0 +reset_vector: + .byte 0xea # jmp to f000:fc00, where IPL + .word 0xfc00, 0xf000 # starts in Standard Flash +#else /* !STD_FLASH i.e. DoC Mil */ +#if (USE_DOC_MIL == 1) + .org 0x1f0 +#elif (USE_DOC_2000_TSOP == 1) || (USE_DOC_MIL_PLUS == 1) + .org 0x3f0 +#endif +reset_vector: + .byte 0xea # jmp to fe00:0000, where IPL + .word 0x0000, DOC_WIN_SEG # starts in DoC +#endif /* STD_FLASH */ + +spl_vector: + .byte 0xea # jmp to 8000:0000, where SPL + .word 0x0000, SPL_RAM_SEG # (LinuxBIOS) starts in RAM + +/* -----------------------------------------------------------------------------------------*/ + +#ifdef STD_FLASH + .org 0xffff +#else /* !STD_FLASH i.e. DoC Mil */ +#if (USE_DOC_MIL == 1) + .org 0x1ff +#elif (USE_DOC_2000_TSOP == 1) || (USE_DOC_MIL_PLUS == 1) + .org 0x3ff +#endif +#endif + +end: + hlt diff --git a/src/mainboard/bcm/e100/ipl.h b/src/mainboard/bcm/e100/ipl.h new file mode 100644 index 0000000000..642b0a9a06 --- /dev/null +++ b/src/mainboard/bcm/e100/ipl.h @@ -0,0 +1,42 @@ +#define PCI_COMMAND_PORT 0xcf8 +#define PCI_DATA_PORT 0xcfc + +#define NORTH_BRIDGE_BASE_ADDR 0x80000000 +#define LPC_BRIDGE_BASE_ADDR 0x80000800 + +#define SMB_BASE_ADDR 0x5080 + +#define DOC_WIN_SEG 0xfe00 +#define DOC_STACK_SEG 0x0400 +#define SPL_RAM_SEG 0x8000 + +#if (USE_DOC_2000_TSOP == 1) +#define DOC_SPL_START_PAGE 4 /* 0-3 for IPL (each of 1KB size) */ +#else /* defined (USE_DOC_MIL) */ +#define DOC_SPL_START_PAGE 2 /* 0,1 for IPL (each of 512B size) */ +#endif + +#define DOC_SPL_SIZE_IN_PAGE 128 - DOC_SPL_START_PAGE /* 1 page = 512 bytes, total 63kB */ + +#define RET_LABEL(label) \ + jmp label##_done + +#define CALL_LABEL(label) \ + jmp label ;\ +label##_done: + +#define CALL_SP(func) \ + lea 0f, %sp ; \ + jmp func ; \ +0: + +#define RET_SP \ + jmp *%sp + +#define CALL_BP(func) \ + lea 0f, %bp ; \ + jmp func ; \ +0: + +#define RET_BP \ + jmp *%bp diff --git a/src/mainboard/bcm/e100/irq_tables.c b/src/mainboard/bcm/e100/irq_tables.c new file mode 100644 index 0000000000..6c281b6e48 --- /dev/null +++ b/src/mainboard/bcm/e100/irq_tables.c @@ -0,0 +1,31 @@ +#include + +#define CHECKSUM 0x1F +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32+16*6, /* there can be total 6 devices on the bus */ + 0x00, /* Bus 0 */ + 0x08, /* Device 1, Function 0 */ + 0x0C20, /* reserve IRQ 11, 10, 5, for PCI */ + 0x1039, /* Silicon Integrated System */ + 0x0008, /* SiS 85C503/5513 ISA Bridge */ + 0x00, /* u8 miniport_data - "crap" */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + CHECKSUM, /* u8 checksum - mod 256 checksum must give zero */ + { + /* bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00, 0x48, {{0x42, 0xdef8}, {0x43, 0xdef8}, {0x44, 0xdef8}, {0x41, 0xdef8}}, + 0x01, 0x00}, + {0x00, 0x58, {{0x43, 0xdef8}, {0x44, 0xdef8}, {0x41, 0xdef8}, {0x42, 0xdef8}}, + 0x02, 0x00}, + {0x00, 0x68, {{0x41, 0xdef8}, {0x42, 0xdef8}, {0x43, 0xdef8}, {0x44, 0xdef8}}, + 0x03, 0x00}, + {0x00, 0x01, {{0x61, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, + 0x00, 0x00}, + {0x00, 0x10, {{0x41, 0xdef8}, {0x42, 0xdef8}, {0x43, 0xdef8}, {0x44, 0xdef8}}, + 0x00, 0x00}, + {0x00, 0x0a, {{0x41, 0xdef8}, {0x42, 0xdef8}, {0x43, 0xdef8}, {0x44, 0xdef8}}, + 0x00, 0x00}, + } +}; diff --git a/src/mainboard/bcm/e100/mainboard.c b/src/mainboard/bcm/e100/mainboard.c new file mode 100644 index 0000000000..c5148a8702 --- /dev/null +++ b/src/mainboard/bcm/e100/mainboard.c @@ -0,0 +1,16 @@ +#include + +void +mainboard_fixup(void) +{ +} + +void +final_mainboard_fixup(void) +{ + void final_southbridge_fixup(void); + + printk_info("SiS 550 (and similar)..."); + + final_southbridge_fixup(); +} diff --git a/util/config/bcm-e100.config b/util/config/bcm-e100.config new file mode 100644 index 0000000000..38219f8e4c --- /dev/null +++ b/util/config/bcm-e100.config @@ -0,0 +1,43 @@ +# Sample config file for SiS 550 SoC with DoC Millennium (as root) +# This will make a target directory of ./winfast +target bcm-e100 + +# SiS 550 SoC demo mainboard +mainboard bcm/e100 + +# Use 256KB Standard Flash as Normal BIOS +option USE_GENERIC_ROM=1 +option STD_FLASH +option ZKERNEL_START=0xfffc0000 + +# payload size = 192KB +option PAYLOAD_SIZE=196608 +# Rom image size = 63KB +option ROM_IMAGE_SIZE=64512 + +# We reuse docipl from DoC +docipl mainboard/bcm/e100/ipl.S + +# Use the internal VGA frame buffer device +option HAVE_FRAMEBUFFER + +# use ELF Loader to load Etherboot +option USE_ELF_BOOT=1 + +# Use etherboot as our payload +payload /home/ollie/work/etherboot/src/bin32/sis900.ebi + +# Add our own special make rules to handle 256KB flash with docipl +makerule romimage: linuxbios.rom payload.block docipl ; +addaction romimage cat payload.block linuxbios.rom docipl.bin > romimage + +makerule docipl: ipl.o ; +addaction docipl objcopy -O binary -R .note -R .comment -S ipl.o docipl +addaction docipl dd if=docipl skip=126 of=docipl.bin +addaction clean rm -f docipl.bin + +makerule linuxbios.rom: linuxbios.strip ; +addaction linuxbios.rom dd if=linuxbios.strip of=linuxbios.rom bs=$(ROM_IMAGE_SIZE) conv=sync + +# Kernel command line parameters +commandline root=/dev/hda1 console=tty0 video=sisfb:1024x768-32@85,font:VGA8x16