Updated winbond configuration.
This commit is contained in:
Greg Watson
parent
1a900329b0
commit
953dc45976
2 changed files with 113 additions and 77 deletions
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@ -61,11 +61,11 @@ void southbridge_early_init(void)
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/*
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* Set ISA memory space
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*/
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pci_direct_ppc.read_byte(0, 0x58, WINBOND_IPADCR, ®8);
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pci_direct_ppc.read_byte(0, 0x58, W83C553F_IPADCR, ®8);
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/* 16 MB ISA memory space */
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reg8 |= (IPADCR_IPATOM4 | IPADCR_IPATOM5 | IPADCR_IPATOM6 | IPADCR_IPATOM7);
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reg8 &= ~IPADCR_MBE512;
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pci_direct_ppc.write_byte(0, 0x58, WINBOND_IPADCR, ®8);
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reg8 |= (W83C553F_IPADCR_IPATOM4 | W83C553F_IPADCR_IPATOM5 | W83C553F_IPADCR_IPATOM6 | W83C553F_IPADCR_IPATOM7);
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reg8 &= ~W83C553F_IPADCR_MBE512;
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pci_direct_ppc.write_byte(0, 0x58, W83C553F_IPADCR, ®8);
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}
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void southbridge_init(void)
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@ -94,30 +94,32 @@ void southbridge_init(void)
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/*
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* Set ISA memory space
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*/
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pci_read_config_byte(devbusfn, WINBOND_IPADCR, ®8);
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pci_read_config_byte(devbusfn, W83C553F_IPADCR, ®8);
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/* 16 MB ISA memory space */
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reg8 |= (IPADCR_IPATOM4 | IPADCR_IPATOM5 | IPADCR_IPATOM6 | IPADCR_IPATOM7);
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reg8 &= ~IPADCR_MBE512;
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pci_write_config_byte(devbusfn, WINBOND_IPADCR, reg8);
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reg8 |= (W83C553F_IPADCR_IPATOM4 | W83C553F_IPADCR_IPATOM5 | W83C553F_IPADCR_IPATOM6 | W83C553F_IPADCR_IPATOM7);
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reg8 &= ~W83C553F_IPADCR_MBE512;
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pci_write_config_byte(devbusfn, W83C553F_IPADCR, reg8);
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/*
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* Chip select: switch off BIOS write protection
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*/
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pci_read_config_byte(devbusfn, WINBOND_CSCR, ®8);
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reg8 |= CSCR_UBIOSCSE;
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reg8 &= ~CSCR_BIOSWP;
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pci_write_config_byte(devbusfn, WINBOND_CSCR, reg8);
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pci_read_config_byte(devbusfn, W83C553F_CSCR, ®8);
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reg8 |= W83C553F_CSCR_UBIOSCSE;
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reg8 &= ~W83C553F_CSCR_BIOSWP;
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pci_write_config_byte(devbusfn, W83C553F_CSCR, reg8);
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/*
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* Interrupt routing:
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* - IDE -> 9/0
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* - INTA -> IRQ 10
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* - INTB -> IRQ 11
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* - INTC -> IRQ 14
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* - INTD -> IRQ 15
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* Enable Port 92
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*/
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pci_write_config_byte(devbusfn, WINBOND_IDEIRCR, 0x90);
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pci_write_config_word(devbusfn, WINBOND_PCIIRCR, 0xABEF);
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reg8 = W83C553F_ATSCR_P92E | W83C553F_ATSCR_KRCEE;
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pci_write_config_byte(devbusfn, W83C553F_CSCR, reg8);
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/*
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* Route IDE interrupts to IRQ 14 & 15 on 8259.
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*/
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pci_write_config_byte(devbusfn, W83C553F_IDEIRCR, 0xef);
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pci_write_config_word(devbusfn, W83C553F_PCIIRCR, 0x0000);
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/*
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* Read IDE bus offsets from function 1 device.
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@ -131,20 +133,37 @@ void southbridge_init(void)
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}
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/*
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* Switch off legacy IRQ for IDE and IDE port 1.
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* Enable native mode on IDE ports and set base address.
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*/
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pci_write_config_byte(devbusfn, 0x09, 0x8F);
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reg8 = W83C553F_PIR_P1NL | W83C553F_PIR_P0NL;
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pci_write_config_byte(devbusfn, W83C553F_PIR, reg8);
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pci_write_config_dword(devbusfn, PCI_BASE_ADDRESS_0, 0xffffffff);
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pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, ®32);
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pci_write_config_dword(devbusfn, PCI_BASE_ADDRESS_0, 0x1f0);
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pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, ®32);
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pci_write_config_dword(devbusfn, PCI_BASE_ADDRESS_1, 0xffffffff);
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pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, ®32);
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pci_write_config_dword(devbusfn, PCI_BASE_ADDRESS_1, 0x3f6);
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pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, ®32);
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pci_write_config_dword(devbusfn, PCI_BASE_ADDRESS_2, 0xffffffff);
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pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_2, ®32);
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pci_write_config_dword(devbusfn, PCI_BASE_ADDRESS_2, 0x170);
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pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_2, ®32);
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pci_write_config_dword(devbusfn, PCI_BASE_ADDRESS_3, 0xffffffff);
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pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_3, ®32);
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pci_write_config_dword(devbusfn, PCI_BASE_ADDRESS_3, 0x376);
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pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_3, ®32);
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/*
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* Set LEGIRQ (IDE->IRQD/E)
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* Disable secondary port ~P1EN (?)
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* Secondary port Mode 0 ~P1F16
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* Set read-ahead duration to 0xff
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* Enable P0 and P1
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*/
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pci_read_config_dword(devbusfn, WINDOND_IDECSR, ®32);
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reg32 &= ~(IDECSR_LEGIRQ | IDECSR_P1EN | IDECSR_P1F16);
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pci_write_config_dword(devbusfn, WINDOND_IDECSR, reg32);
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reg32 = 0x00ff0000 | W83C553F_IDECSR_P1EN | W83C553F_IDECSR_P0EN;
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pci_write_config_dword(devbusfn, W83C553F_IDECSR, reg32);
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pci_read_config_dword(devbusfn, W83C553F_IDECSR, ®32);
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pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &ide_bus_offset[0]);
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printk_debug("ide bus offset = 0x%x\n", ide_bus_offset[0]);
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ide_bus_offset[0] &= ~1;
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#if CONFIG_IDE_MAXBUS > 1
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pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_2, &ide_bus_offset[1]);
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@ -157,6 +176,7 @@ void southbridge_init(void)
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pci_read_config_word(devbusfn, PCI_COMMAND, ®16);
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reg16 |= PCI_COMMAND_MASTER | PCI_COMMAND_IO;
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pci_write_config_word(devbusfn, PCI_COMMAND, reg16);
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pci_read_config_word(devbusfn, PCI_COMMAND, ®16);
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/*
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* Initialise ISA interrupt controller
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@ -173,19 +193,19 @@ void southbridge_init(void)
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void initialise_pic(void)
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{
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outb(W83C553F_PIC1_ICW1, 0x11);
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outb(W83C553F_PIC1_ICW2, 0x08);
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outb(W83C553F_PIC1_ICW3, 0x04);
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outb(W83C553F_PIC1_ICW4, 0x01);
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outb(W83C553F_PIC1_OCW1, 0xfb);
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outb(W83C553F_PIC1_ELC, 0x20);
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outb(W83C553F_PIC1_ICW1, 0x11); /* start init sequence, ICW4 needed */
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outb(W83C553F_PIC1_ICW2, 0x08); /* base address 00001 */
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outb(W83C553F_PIC1_ICW3, 0x04); /* slave on IRQ2 */
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outb(W83C553F_PIC1_ICW4, 0x01); /* x86 mode */
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outb(W83C553F_PIC1_OCW1, 0xfb); /* enable IRQ 2 */
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outb(W83C553F_PIC1_ELC, 0xf8); /* all IRQ's edge sensitive */
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outb(W83C553F_PIC2_ICW1, 0x11);
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outb(W83C553F_PIC2_ICW2, 0x08);
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outb(W83C553F_PIC2_ICW3, 0x02);
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outb(W83C553F_PIC2_ICW4, 0x01);
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outb(W83C553F_PIC2_OCW1, 0xff);
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outb(W83C553F_PIC2_ELC, 0xce);
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outb(W83C553F_PIC2_ICW1, 0x11); /* start init sequence, ICW4 needed */
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outb(W83C553F_PIC2_ICW2, 0x08); /* base address 00001 */
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outb(W83C553F_PIC2_ICW3, 0x02); /* slave ID 2 */
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outb(W83C553F_PIC2_ICW4, 0x01); /* x86 mode */
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outb(W83C553F_PIC2_OCW1, 0xff); /* disable all IRQ's */
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outb(W83C553F_PIC2_ELC, 0xde); /* all IRQ's edge sensitive */
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outb(W83C553F_TMR1_CMOD, 0x74);
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@ -34,42 +34,58 @@
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#define W83C553F_DID 0x0565
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#define W83C553F_IDE 0x0105
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#define WINBOND_PCICONTR 0x40 /*pci control reg*/
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#define WINBOND_SGBAR 0x41 /*scatter/gather base address reg*/
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#define WINBOND_LBCR 0x42 /*Line Buffer Control reg*/
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#define WINBOND_IDEIRCR 0x43 /*IDE Interrupt Routing Control Reg*/
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#define WINBOND_PCIIRCR 0x44 /*PCI Interrupt Routing Control Reg*/
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#define WINBOND_BTBAR 0x46 /*BIOS Timer Base Address Register*/
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#define WINBOND_IPADCR 0x48 /*ISA to PCI Address Decoder Control Register*/
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#define WINBOND_IRADCR 0x49 /*ISA ROM Address Decoder Control Register*/
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#define WINBOND_IPMHSAR 0x4a /*ISA to PCI Memory Hole STart Address Register*/
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#define WINBOND_IPMHSR 0x4b /*ISA to PCI Memory Hols Size Register*/
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#define WINBOND_CDR 0x4c /*Clock Divisor Register*/
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#define WINBOND_CSCR 0x4d /*Chip Select Control Register*/
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#define WINBOND_ATSCR 0x4e /*AT System Control register*/
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#define WINBOND_ATBCR 0x4f /*AT Bus ControL Register*/
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#define WINBOND_IRQBEE0R 0x60 /*IRQ Break Event Enable 0 Register*/
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#define WINBOND_IRQBEE1R 0x61 /*IRQ Break Event Enable 1 Register*/
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#define WINBOND_ABEER 0x62 /*Additional Break Event Enable Register*/
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#define WINBOND_DMABEER 0x63 /*DMA Break Event Enable Register*/
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/* Function 0 registers */
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#define W83C553F_PCICONTR 0x40 /*pci control reg*/
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#define W83C553F_SGBAR 0x41 /*scatter/gather base address reg*/
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#define W83C553F_LBCR 0x42 /*Line Buffer Control reg*/
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#define W83C553F_IDEIRCR 0x43 /*IDE Interrupt Routing Control Reg*/
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#define W83C553F_PCIIRCR 0x44 /*PCI Interrupt Routing Control Reg*/
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#define W83C553F_BTBAR 0x46 /*BIOS Timer Base Address Register*/
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#define W83C553F_IPADCR 0x48 /*ISA to PCI Address Decoder Control Register*/
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#define W83C553F_IRADCR 0x49 /*ISA ROM Address Decoder Control Register*/
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#define W83C553F_IPMHSAR 0x4a /*ISA to PCI Memory Hole STart Address Register*/
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#define W83C553F_IPMHSR 0x4b /*ISA to PCI Memory Hols Size Register*/
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#define W83C553F_CDR 0x4c /*Clock Divisor Register*/
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#define W83C553F_CSCR 0x4d /*Chip Select Control Register*/
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#define W83C553F_ATSCR 0x4e /*AT System Control register*/
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#define W83C553F_ATBCR 0x4f /*AT Bus ControL Register*/
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#define W83C553F_IRQBEE0R 0x60 /*IRQ Break Event Enable 0 Register*/
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#define W83C553F_IRQBEE1R 0x61 /*IRQ Break Event Enable 1 Register*/
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#define W83C553F_ABEER 0x62 /*Additional Break Event Enable Register*/
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#define W83C553F_DMABEER 0x63 /*DMA Break Event Enable Register*/
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#define WINDOND_IDECSR 0x40 /*IDE Control/Status Register, Function 1*/
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/* Function 1 registers */
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#define W83C553F_PIR 0x09 /*Programming Interface Register*/
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#define W83C553F_IDECSR 0x40 /*IDE Control/Status Register*/
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#define IPADCR_MBE512 0x1
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#define IPADCR_MBE640 0x2
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#define IPADCR_IPATOM4 0x10
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#define IPADCR_IPATOM5 0x20
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#define IPADCR_IPATOM6 0x40
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#define IPADCR_IPATOM7 0x80
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/* register bit definitions */
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#define W83C553F_IPADCR_MBE512 0x1
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#define W83C553F_IPADCR_MBE640 0x2
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#define W83C553F_IPADCR_IPATOM4 0x10
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#define W83C553F_IPADCR_IPATOM5 0x20
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#define W83C553F_IPADCR_IPATOM6 0x40
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#define W83C553F_IPADCR_IPATOM7 0x80
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#define CSCR_UBIOSCSE 0x10
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#define CSCR_BIOSWP 0x20
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#define W83C553F_CSCR_UBIOSCSE 0x10
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#define W83C553F_CSCR_BIOSWP 0x20
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#define IDECSR_P0EN 0x01
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#define IDECSR_P0F16 0x02
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#define IDECSR_P1EN 0x10
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#define IDECSR_P1F16 0x20
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#define IDECSR_LEGIRQ 0x800
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#define W83C553F_IDECSR_P0EN 0x01
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#define W83C553F_IDECSR_P0F16 0x02
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#define W83C553F_IDECSR_P1EN 0x10
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#define W83C553F_IDECSR_P1F16 0x20
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#define W83C553F_IDECSR_LEGIRQ 0x800
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#define W83C553F_ATSCR_ISARE 0x40
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#define W83C553F_ATSCR_FERRE 0x10
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#define W83C553F_ATSCR_P92E 0x04
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#define W83C553F_ATSCR_KRCEE 0x02
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#define W83C553F_ATSCR_KGA20EE 0x01
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#define W83C553F_PIR_BM 0x80
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#define W83C553F_PIR_P1PROG 0x08
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#define W83C553F_PIR_P1NL 0x04
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#define W83C553F_PIR_P0PROG 0x02
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#define W83C553F_PIR_P0NL 0x01
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/*
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* Interrupt controller
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