diff --git a/src/southbridge/winbond/w83c553/w83c553f.c b/src/southbridge/winbond/w83c553/w83c553f.c index 1c00578ab1..699089200f 100644 --- a/src/southbridge/winbond/w83c553/w83c553f.c +++ b/src/southbridge/winbond/w83c553/w83c553f.c @@ -61,11 +61,11 @@ void southbridge_early_init(void) /* * Set ISA memory space */ - pci_direct_ppc.read_byte(0, 0x58, WINBOND_IPADCR, ®8); + pci_direct_ppc.read_byte(0, 0x58, W83C553F_IPADCR, ®8); /* 16 MB ISA memory space */ - reg8 |= (IPADCR_IPATOM4 | IPADCR_IPATOM5 | IPADCR_IPATOM6 | IPADCR_IPATOM7); - reg8 &= ~IPADCR_MBE512; - pci_direct_ppc.write_byte(0, 0x58, WINBOND_IPADCR, ®8); + reg8 |= (W83C553F_IPADCR_IPATOM4 | W83C553F_IPADCR_IPATOM5 | W83C553F_IPADCR_IPATOM6 | W83C553F_IPADCR_IPATOM7); + reg8 &= ~W83C553F_IPADCR_MBE512; + pci_direct_ppc.write_byte(0, 0x58, W83C553F_IPADCR, ®8); } void southbridge_init(void) @@ -94,30 +94,32 @@ void southbridge_init(void) /* * Set ISA memory space */ - pci_read_config_byte(devbusfn, WINBOND_IPADCR, ®8); + pci_read_config_byte(devbusfn, W83C553F_IPADCR, ®8); /* 16 MB ISA memory space */ - reg8 |= (IPADCR_IPATOM4 | IPADCR_IPATOM5 | IPADCR_IPATOM6 | IPADCR_IPATOM7); - reg8 &= ~IPADCR_MBE512; - pci_write_config_byte(devbusfn, WINBOND_IPADCR, reg8); + reg8 |= (W83C553F_IPADCR_IPATOM4 | W83C553F_IPADCR_IPATOM5 | W83C553F_IPADCR_IPATOM6 | W83C553F_IPADCR_IPATOM7); + reg8 &= ~W83C553F_IPADCR_MBE512; + pci_write_config_byte(devbusfn, W83C553F_IPADCR, reg8); /* * Chip select: switch off BIOS write protection */ - pci_read_config_byte(devbusfn, WINBOND_CSCR, ®8); - reg8 |= CSCR_UBIOSCSE; - reg8 &= ~CSCR_BIOSWP; - pci_write_config_byte(devbusfn, WINBOND_CSCR, reg8); + pci_read_config_byte(devbusfn, W83C553F_CSCR, ®8); + reg8 |= W83C553F_CSCR_UBIOSCSE; + reg8 &= ~W83C553F_CSCR_BIOSWP; + pci_write_config_byte(devbusfn, W83C553F_CSCR, reg8); + /* - * Interrupt routing: - * - IDE -> 9/0 - * - INTA -> IRQ 10 - * - INTB -> IRQ 11 - * - INTC -> IRQ 14 - * - INTD -> IRQ 15 + * Enable Port 92 */ - pci_write_config_byte(devbusfn, WINBOND_IDEIRCR, 0x90); - pci_write_config_word(devbusfn, WINBOND_PCIIRCR, 0xABEF); + reg8 = W83C553F_ATSCR_P92E | W83C553F_ATSCR_KRCEE; + pci_write_config_byte(devbusfn, W83C553F_CSCR, reg8); + + /* + * Route IDE interrupts to IRQ 14 & 15 on 8259. + */ + pci_write_config_byte(devbusfn, W83C553F_IDEIRCR, 0xef); + pci_write_config_word(devbusfn, W83C553F_PCIIRCR, 0x0000); /* * Read IDE bus offsets from function 1 device. @@ -131,20 +133,37 @@ void southbridge_init(void) } /* - * Switch off legacy IRQ for IDE and IDE port 1. + * Enable native mode on IDE ports and set base address. */ - pci_write_config_byte(devbusfn, 0x09, 0x8F); + reg8 = W83C553F_PIR_P1NL | W83C553F_PIR_P0NL; + pci_write_config_byte(devbusfn, W83C553F_PIR, reg8); + pci_write_config_dword(devbusfn, PCI_BASE_ADDRESS_0, 0xffffffff); + pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, ®32); + pci_write_config_dword(devbusfn, PCI_BASE_ADDRESS_0, 0x1f0); + pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, ®32); + pci_write_config_dword(devbusfn, PCI_BASE_ADDRESS_1, 0xffffffff); + pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, ®32); + pci_write_config_dword(devbusfn, PCI_BASE_ADDRESS_1, 0x3f6); + pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, ®32); + pci_write_config_dword(devbusfn, PCI_BASE_ADDRESS_2, 0xffffffff); + pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_2, ®32); + pci_write_config_dword(devbusfn, PCI_BASE_ADDRESS_2, 0x170); + pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_2, ®32); + pci_write_config_dword(devbusfn, PCI_BASE_ADDRESS_3, 0xffffffff); + pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_3, ®32); + pci_write_config_dword(devbusfn, PCI_BASE_ADDRESS_3, 0x376); + pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_3, ®32); /* - * Set LEGIRQ (IDE->IRQD/E) - * Disable secondary port ~P1EN (?) - * Secondary port Mode 0 ~P1F16 + * Set read-ahead duration to 0xff + * Enable P0 and P1 */ - pci_read_config_dword(devbusfn, WINDOND_IDECSR, ®32); - reg32 &= ~(IDECSR_LEGIRQ | IDECSR_P1EN | IDECSR_P1F16); - pci_write_config_dword(devbusfn, WINDOND_IDECSR, reg32); + reg32 = 0x00ff0000 | W83C553F_IDECSR_P1EN | W83C553F_IDECSR_P0EN; + pci_write_config_dword(devbusfn, W83C553F_IDECSR, reg32); + pci_read_config_dword(devbusfn, W83C553F_IDECSR, ®32); pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &ide_bus_offset[0]); + printk_debug("ide bus offset = 0x%x\n", ide_bus_offset[0]); ide_bus_offset[0] &= ~1; #if CONFIG_IDE_MAXBUS > 1 pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_2, &ide_bus_offset[1]); @@ -157,6 +176,7 @@ void southbridge_init(void) pci_read_config_word(devbusfn, PCI_COMMAND, ®16); reg16 |= PCI_COMMAND_MASTER | PCI_COMMAND_IO; pci_write_config_word(devbusfn, PCI_COMMAND, reg16); + pci_read_config_word(devbusfn, PCI_COMMAND, ®16); /* * Initialise ISA interrupt controller @@ -173,19 +193,19 @@ void southbridge_init(void) void initialise_pic(void) { - outb(W83C553F_PIC1_ICW1, 0x11); - outb(W83C553F_PIC1_ICW2, 0x08); - outb(W83C553F_PIC1_ICW3, 0x04); - outb(W83C553F_PIC1_ICW4, 0x01); - outb(W83C553F_PIC1_OCW1, 0xfb); - outb(W83C553F_PIC1_ELC, 0x20); + outb(W83C553F_PIC1_ICW1, 0x11); /* start init sequence, ICW4 needed */ + outb(W83C553F_PIC1_ICW2, 0x08); /* base address 00001 */ + outb(W83C553F_PIC1_ICW3, 0x04); /* slave on IRQ2 */ + outb(W83C553F_PIC1_ICW4, 0x01); /* x86 mode */ + outb(W83C553F_PIC1_OCW1, 0xfb); /* enable IRQ 2 */ + outb(W83C553F_PIC1_ELC, 0xf8); /* all IRQ's edge sensitive */ - outb(W83C553F_PIC2_ICW1, 0x11); - outb(W83C553F_PIC2_ICW2, 0x08); - outb(W83C553F_PIC2_ICW3, 0x02); - outb(W83C553F_PIC2_ICW4, 0x01); - outb(W83C553F_PIC2_OCW1, 0xff); - outb(W83C553F_PIC2_ELC, 0xce); + outb(W83C553F_PIC2_ICW1, 0x11); /* start init sequence, ICW4 needed */ + outb(W83C553F_PIC2_ICW2, 0x08); /* base address 00001 */ + outb(W83C553F_PIC2_ICW3, 0x02); /* slave ID 2 */ + outb(W83C553F_PIC2_ICW4, 0x01); /* x86 mode */ + outb(W83C553F_PIC2_OCW1, 0xff); /* disable all IRQ's */ + outb(W83C553F_PIC2_ELC, 0xde); /* all IRQ's edge sensitive */ outb(W83C553F_TMR1_CMOD, 0x74); diff --git a/src/southbridge/winbond/w83c553/w83c553f.h b/src/southbridge/winbond/w83c553/w83c553f.h index b0f5bbf19a..f071371938 100644 --- a/src/southbridge/winbond/w83c553/w83c553f.h +++ b/src/southbridge/winbond/w83c553/w83c553f.h @@ -34,42 +34,58 @@ #define W83C553F_DID 0x0565 #define W83C553F_IDE 0x0105 -#define WINBOND_PCICONTR 0x40 /*pci control reg*/ -#define WINBOND_SGBAR 0x41 /*scatter/gather base address reg*/ -#define WINBOND_LBCR 0x42 /*Line Buffer Control reg*/ -#define WINBOND_IDEIRCR 0x43 /*IDE Interrupt Routing Control Reg*/ -#define WINBOND_PCIIRCR 0x44 /*PCI Interrupt Routing Control Reg*/ -#define WINBOND_BTBAR 0x46 /*BIOS Timer Base Address Register*/ -#define WINBOND_IPADCR 0x48 /*ISA to PCI Address Decoder Control Register*/ -#define WINBOND_IRADCR 0x49 /*ISA ROM Address Decoder Control Register*/ -#define WINBOND_IPMHSAR 0x4a /*ISA to PCI Memory Hole STart Address Register*/ -#define WINBOND_IPMHSR 0x4b /*ISA to PCI Memory Hols Size Register*/ -#define WINBOND_CDR 0x4c /*Clock Divisor Register*/ -#define WINBOND_CSCR 0x4d /*Chip Select Control Register*/ -#define WINBOND_ATSCR 0x4e /*AT System Control register*/ -#define WINBOND_ATBCR 0x4f /*AT Bus ControL Register*/ -#define WINBOND_IRQBEE0R 0x60 /*IRQ Break Event Enable 0 Register*/ -#define WINBOND_IRQBEE1R 0x61 /*IRQ Break Event Enable 1 Register*/ -#define WINBOND_ABEER 0x62 /*Additional Break Event Enable Register*/ -#define WINBOND_DMABEER 0x63 /*DMA Break Event Enable Register*/ +/* Function 0 registers */ +#define W83C553F_PCICONTR 0x40 /*pci control reg*/ +#define W83C553F_SGBAR 0x41 /*scatter/gather base address reg*/ +#define W83C553F_LBCR 0x42 /*Line Buffer Control reg*/ +#define W83C553F_IDEIRCR 0x43 /*IDE Interrupt Routing Control Reg*/ +#define W83C553F_PCIIRCR 0x44 /*PCI Interrupt Routing Control Reg*/ +#define W83C553F_BTBAR 0x46 /*BIOS Timer Base Address Register*/ +#define W83C553F_IPADCR 0x48 /*ISA to PCI Address Decoder Control Register*/ +#define W83C553F_IRADCR 0x49 /*ISA ROM Address Decoder Control Register*/ +#define W83C553F_IPMHSAR 0x4a /*ISA to PCI Memory Hole STart Address Register*/ +#define W83C553F_IPMHSR 0x4b /*ISA to PCI Memory Hols Size Register*/ +#define W83C553F_CDR 0x4c /*Clock Divisor Register*/ +#define W83C553F_CSCR 0x4d /*Chip Select Control Register*/ +#define W83C553F_ATSCR 0x4e /*AT System Control register*/ +#define W83C553F_ATBCR 0x4f /*AT Bus ControL Register*/ +#define W83C553F_IRQBEE0R 0x60 /*IRQ Break Event Enable 0 Register*/ +#define W83C553F_IRQBEE1R 0x61 /*IRQ Break Event Enable 1 Register*/ +#define W83C553F_ABEER 0x62 /*Additional Break Event Enable Register*/ +#define W83C553F_DMABEER 0x63 /*DMA Break Event Enable Register*/ -#define WINDOND_IDECSR 0x40 /*IDE Control/Status Register, Function 1*/ +/* Function 1 registers */ +#define W83C553F_PIR 0x09 /*Programming Interface Register*/ +#define W83C553F_IDECSR 0x40 /*IDE Control/Status Register*/ -#define IPADCR_MBE512 0x1 -#define IPADCR_MBE640 0x2 -#define IPADCR_IPATOM4 0x10 -#define IPADCR_IPATOM5 0x20 -#define IPADCR_IPATOM6 0x40 -#define IPADCR_IPATOM7 0x80 +/* register bit definitions */ +#define W83C553F_IPADCR_MBE512 0x1 +#define W83C553F_IPADCR_MBE640 0x2 +#define W83C553F_IPADCR_IPATOM4 0x10 +#define W83C553F_IPADCR_IPATOM5 0x20 +#define W83C553F_IPADCR_IPATOM6 0x40 +#define W83C553F_IPADCR_IPATOM7 0x80 -#define CSCR_UBIOSCSE 0x10 -#define CSCR_BIOSWP 0x20 +#define W83C553F_CSCR_UBIOSCSE 0x10 +#define W83C553F_CSCR_BIOSWP 0x20 -#define IDECSR_P0EN 0x01 -#define IDECSR_P0F16 0x02 -#define IDECSR_P1EN 0x10 -#define IDECSR_P1F16 0x20 -#define IDECSR_LEGIRQ 0x800 +#define W83C553F_IDECSR_P0EN 0x01 +#define W83C553F_IDECSR_P0F16 0x02 +#define W83C553F_IDECSR_P1EN 0x10 +#define W83C553F_IDECSR_P1F16 0x20 +#define W83C553F_IDECSR_LEGIRQ 0x800 + +#define W83C553F_ATSCR_ISARE 0x40 +#define W83C553F_ATSCR_FERRE 0x10 +#define W83C553F_ATSCR_P92E 0x04 +#define W83C553F_ATSCR_KRCEE 0x02 +#define W83C553F_ATSCR_KGA20EE 0x01 + +#define W83C553F_PIR_BM 0x80 +#define W83C553F_PIR_P1PROG 0x08 +#define W83C553F_PIR_P1NL 0x04 +#define W83C553F_PIR_P0PROG 0x02 +#define W83C553F_PIR_P0NL 0x01 /* * Interrupt controller