From 94d200c3940fc9781074df2fe734e263d4c57644 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Tue, 3 Dec 2024 09:49:24 +0100 Subject: [PATCH] soc/intel/xeon_sp/cpx: Add missing FADT fields CPX uses the same PCH as SKX does, thus it has the same ACPI timer timer and PM2 control fields as SKX. Copy the code from skx to cpx to reduce code differences. Allows to merge both codebases into one. Change-Id: I92fc63a6655fb915b2c06273c3259dddfb93e8bb Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/85508 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/soc/intel/xeon_sp/cpx/soc_acpi.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/xeon_sp/cpx/soc_acpi.c b/src/soc/intel/xeon_sp/cpx/soc_acpi.c index c7edb22e6c..defc69d898 100644 --- a/src/soc/intel/xeon_sp/cpx/soc_acpi.c +++ b/src/soc/intel/xeon_sp/cpx/soc_acpi.c @@ -36,8 +36,22 @@ uint32_t soc_read_sci_irq_select(void) void soc_fill_fadt(acpi_fadt_t *fadt) { - /* Clear flags set by common/block/acpi/acpi.c acpi_fill_fadt() */ - fadt->flags &= ~(ACPI_FADT_SEALED_CASE | ACPI_FADT_S4_RTC_WAKE); + const uint16_t pmbase = ACPI_BASE_ADDRESS; + + /* Fix flags set by common/block/acpi/acpi.c acpi_fill_fadt() */ + fadt->flags &= ~(ACPI_FADT_SEALED_CASE); + fadt->flags |= ACPI_FADT_SLEEP_TYPE; + + fadt->pm2_cnt_blk = pmbase + PM2_CNT; + fadt->pm_tmr_blk = pmbase + PM1_TMR; + + fadt->pm2_cnt_len = 1; + fadt->pm_tmr_len = 4; + + fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES; + + /* PM Extended Registers */ + fill_fadt_extended_pm_io(fadt); } void soc_power_states_generation(int core_id, int cores_per_package)