From 901cac7c3c0740eb689a716d85e2e34b14dfaa79 Mon Sep 17 00:00:00 2001 From: Sean Rhodes Date: Thu, 5 Feb 2026 12:20:44 +0000 Subject: [PATCH] x86/mtrr: Avoid WC for VGA BARs above 4GiB On Arrow Lake we ran out of variable MTRRs, leaving PCI BARs uncached. This made the edk2 setup UI extremely slow due to UC MMIO/framebuffer writes. Ensure BAR ranges get a cacheable attribute instead of falling back to UC. Change-Id: I74a89cf334d1eb74bbfbb4b0f9621f098bfa4a89 Signed-off-by: Sean Rhodes Reviewed-on: https://review.coreboot.org/c/coreboot/+/91109 Reviewed-by: Patrick Rudolph Tested-by: build bot (Jenkins) --- src/cpu/x86/mtrr/mtrr.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index 72727861de..001f9b5a88 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -122,6 +122,16 @@ static int filter_vga_wrcomb(struct device *dev, struct resource *res) if (((dev->class >> 8) != PCI_CLASS_DISPLAY_VGA)) return 0; + /* + * Only mark 32-bit BARs as WC. Some platforms expose additional large + * prefetchable BARs above 4GiB for the iGPU, and tagging those as WC + * can fragment the address space enough to exhaust variable MTRRs. + * Keeping the below-4GiB framebuffer WC is the priority for payload UI + * performance. + */ + if (res->size != 0 && res->base >= 0x100000000ULL) + return 0; + /* Add resource as write-combining in the address space. */ return 1; }